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X-CSE-ConnectionGUID: Hp4kxJpaRTCymIeX9dtyVA== X-CSE-MsgGUID: zv8ACbsASb2xAfuzqroHmg== X-IronPort-AV: E=McAfee;i="6800,10657,11705"; a="76350407" X-IronPort-AV: E=Sophos;i="6.21,298,1763452800"; d="scan'208";a="76350407" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2026 09:01:16 -0800 X-CSE-ConnectionGUID: 3R/4+a1uTQG8erTQBNn2bA== X-CSE-MsgGUID: fTYC+iGuRIOHPY0G4Ao1AA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,298,1763452800"; d="scan'208";a="213484767" Received: from sghuge-mobl2.amr.corp.intel.com (HELO [10.125.109.224]) ([10.125.109.224]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2026 09:01:16 -0800 Message-ID: Date: Wed, 18 Feb 2026 09:01:15 -0800 Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/6] x86/sev: add support for enabling RMPOPT To: "Kalra, Ashish" , K Prateek Nayak , tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, seanjc@google.com, peterz@infradead.org, thomas.lendacky@amd.com, herbert@gondor.apana.org.au, davem@davemloft.net, ardb@kernel.org Cc: pbonzini@redhat.com, aik@amd.com, Michael.Roth@amd.com, Tycho.Andersen@amd.com, Nathan.Fontenot@amd.com, jackyli@google.com, pgonda@google.com, rientjes@google.com, jacobhxu@google.com, xin@zytor.com, pawan.kumar.gupta@linux.intel.com, babu.moger@amd.com, dyoung@redhat.com, nikunj@amd.com, john.allen@amd.com, darwi@linutronix.de, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, kvm@vger.kernel.org, linux-coco@lists.linux.dev References: <7df872903e16ccee9fce73b34280ede8dfc37063.1771321114.git.ashish.kalra@amd.com> <10baddd3-add6-4771-a1ce-f759d3ec69d2@intel.com> <59c0b0f0-26b0-4311-82a9-a5f8392ec4c6@intel.com> <4e912046-8ae0-4cb2-b2cb-11c754df7536@amd.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 2/18/26 08:55, Kalra, Ashish wrote: > Because, setting RMPOPT_BASE MSR (which is a per-core MSR) and > RMPOPT instruction need to be issued on only one thread per core. If > the primary thread is offlined and secondary thread is not > considered, we will miss/skip setting either the RMPOPT_BASE MSR or > not issuing the RMPOPT instruction for that physical CPU, which > means no RMP optimizations enabled for that physical CPU. What is the harm of issuing it twice per core?