* Re: [PATCH v3 6/8] hwrng: amd: Replace global variable with private struct
From: Jason Cooper @ 2016-08-27 14:43 UTC (permalink / raw)
To: LABBE Corentin; +Cc: mpm, herbert, linux-crypto, linux-kernel
In-Reply-To: <1472209896-17197-7-git-send-email-clabbe.montjoie@gmail.com>
Hi Corentin,
On Fri, Aug 26, 2016 at 01:11:34PM +0200, LABBE Corentin wrote:
> Instead of having two global variable, it's better to use a
> private struct. This will permit to remove amd_pdev variable
>
> Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
> ---
> drivers/char/hw_random/amd-rng.c | 57 ++++++++++++++++++++++++++--------------
> 1 file changed, 38 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c
> index 383e197..4ef94e9 100644
> --- a/drivers/char/hw_random/amd-rng.c
> +++ b/drivers/char/hw_random/amd-rng.c
> @@ -47,15 +47,18 @@ static const struct pci_device_id pci_tbl[] = {
> };
> MODULE_DEVICE_TABLE(pci, pci_tbl);
>
> -static struct pci_dev *amd_pdev;
> +struct amd768_priv {
> + struct pci_dev *pcidev;
> + u32 pmbase;
> +};
>
> static int amd_rng_data_present(struct hwrng *rng, int wait)
> {
> - u32 pmbase = (u32)rng->priv;
> + struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
Please remove unnecessary casts...
> int data, i;
>
> for (i = 0; i < 20; i++) {
> - data = !!(inl(pmbase + 0xF4) & 1);
> + data = !!(inl(priv->pmbase + 0xF4) & 1);
> if (data || !wait)
> break;
> udelay(10);
> @@ -65,35 +68,37 @@ static int amd_rng_data_present(struct hwrng *rng, int wait)
>
> static int amd_rng_data_read(struct hwrng *rng, u32 *data)
> {
> - u32 pmbase = (u32)rng->priv;
> + struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
here,
>
> - *data = inl(pmbase + 0xF0);
> + *data = inl(priv->pmbase + 0xF0);
>
> return 4;
> }
>
> static int amd_rng_init(struct hwrng *rng)
> {
> + struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
here,
> u8 rnen;
>
> - pci_read_config_byte(amd_pdev, 0x40, &rnen);
> + pci_read_config_byte(priv->pcidev, 0x40, &rnen);
> rnen |= BIT(7); /* RNG on */
> - pci_write_config_byte(amd_pdev, 0x40, rnen);
> + pci_write_config_byte(priv->pcidev, 0x40, rnen);
>
> - pci_read_config_byte(amd_pdev, 0x41, &rnen);
> + pci_read_config_byte(priv->pcidev, 0x41, &rnen);
> rnen |= BIT(7); /* PMIO enable */
> - pci_write_config_byte(amd_pdev, 0x41, rnen);
> + pci_write_config_byte(priv->pcidev, 0x41, rnen);
>
> return 0;
> }
>
> static void amd_rng_cleanup(struct hwrng *rng)
> {
> + struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
here,
> u8 rnen;
>
> - pci_read_config_byte(amd_pdev, 0x40, &rnen);
> + pci_read_config_byte(priv->pcidev, 0x40, &rnen);
> rnen &= ~BIT(7); /* RNG off */
> - pci_write_config_byte(amd_pdev, 0x40, rnen);
> + pci_write_config_byte(priv->pcidev, 0x40, rnen);
> }
>
> static struct hwrng amd_rng = {
> @@ -110,6 +115,7 @@ static int __init mod_init(void)
> struct pci_dev *pdev = NULL;
> const struct pci_device_id *ent;
> u32 pmbase;
> + struct amd768_priv *priv;
>
> for_each_pci_dev(pdev) {
> ent = pci_match_id(pci_tbl, pdev);
> @@ -117,24 +123,30 @@ static int __init mod_init(void)
> goto found;
> }
> /* Device not found. */
> - goto out;
> + return -ENODEV;
>
> found:
> err = pci_read_config_dword(pdev, 0x58, &pmbase);
> if (err)
> - goto out;
> - err = -EIO;
> + return err;
> +
> pmbase &= 0x0000FF00;
> if (pmbase == 0)
> - goto out;
> + return -EIO;
> +
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> if (!request_region(pmbase + 0xF0, 8, DRV_NAME)) {
> dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
> pmbase + 0xF0);
> err = -EBUSY;
> goto out;
> }
> - amd_rng.priv = (unsigned long)pmbase;
> - amd_pdev = pdev;
> + amd_rng.priv = (unsigned long)priv;
here,
> + priv->pmbase = pmbase;
> + priv->pcidev = pdev;
>
> pr_info(DRV_NAME " detected\n");
> err = hwrng_register(&amd_rng);
> @@ -143,17 +155,24 @@ found:
> release_region(pmbase + 0xF0, 8);
> goto out;
> }
> + return 0;
> +
> out:
> + kfree(priv);
> return err;
> }
>
> static void __exit mod_exit(void)
> {
> - u32 pmbase = (unsigned long)amd_rng.priv;
> + struct amd768_priv *priv;
> +
> + priv = (struct amd768_priv *)amd_rng.priv;
and here.
thx,
Jason.
>
> hwrng_unregister(&amd_rng);
>
> - release_region(pmbase + 0xF0, 8);
> + release_region(priv->pmbase + 0xF0, 8);
> +
> + kfree(priv);
> }
>
> module_init(mod_init);
> --
> 2.7.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-crypto" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: Git bisected regression for ipsec/aead
From: Sowmini Varadhan @ 2016-08-27 10:13 UTC (permalink / raw)
To: Herbert Xu; +Cc: linux-crypto, joshua.a.hay, steffen.klassert
In-Reply-To: <20160825084951.GA11496@gondor.apana.org.au>
On (08/25/16 16:49), Herbert Xu wrote:
>
> On Fri, Aug 19, 2016 at 03:21:24PM -0400, Sowmini Varadhan wrote:
> > 7271b33cb87e80f3a416fb031ad3ca87f0bea80a is the first bad commit
> This bisection doesn't make much sense as this patch just causes
> cryptd to be used a little more more frequently. But it does
> point the finger at cryptd.
On additional testing, I think this might be related to some
subtle race/timing issue so that git-bisect may not necessarily
be able to pin-point the correct bad-commit: if I add a few
printks in other parts of the IPsec stack (and change the timing),
the problem does not reproduce. Let me try to collect more data
on this.
Meanwhile, if you can see some bug in the commit above, then
it probably makes sense to fix it upstream anyway.
--Sowmini
^ permalink raw reply
* caam - IV source for IPsec decryption
From: Horia Ioan Geanta Neag @ 2016-08-25 16:12 UTC (permalink / raw)
To: Herbert Xu; +Cc: linux-crypto@vger.kernel.org
Herbert,
Commits
7021b2e1cddd "esp4: Switch to new AEAD interface"
000ae7b2690e "esp6: Switch to new AEAD interface"
removed the following:
/* Get ivec. This can be wrong, check against another impls. */
iv = esph->enc_data;
from IPsec decryption - esp{4,6}_input(),
so the IV in req->iv received by the implementer is no longer valid.
Thus, the load of IV in caam driver - caamalg.c, init_authenc_job():
if (ivsize && (is_rfc3686 || !(alg->caam.geniv && encrypt)))
append_load_as_imm(desc, req->iv, ivsize,
LDST_CLASS_1_CCB |
LDST_SRCDST_BYTE_CONTEXT |
(ivoffset << LDST_OFFSET_SHIFT));
is not suited for case mentioned above.
Instead, the IV should be read from the req->src scatterlist
(which consists of assoc data, iv, ciphertext).
Please let me know if this is accurate, so I could prepare a fix.
Thanks,
Horia
^ permalink raw reply
* [PATCH] hw_random: Remove check for max less than 4 bytes
From: PrasannaKumar Muralidharan @ 2016-08-26 18:32 UTC (permalink / raw)
To: mpm, herbert, linux-crypto, linux-kernel; +Cc: PrasannaKumar Muralidharan
HW RNG core never asks for data less than 4 bytes. The check whether max
is less than 4 bytes is unnecessary. Remove the check.
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
drivers/char/hw_random/meson-rng.c | 3 ---
drivers/char/hw_random/st-rng.c | 3 ---
2 files changed, 6 deletions(-)
diff --git a/drivers/char/hw_random/meson-rng.c b/drivers/char/hw_random/meson-rng.c
index 0cfd81b..58bef39 100644
--- a/drivers/char/hw_random/meson-rng.c
+++ b/drivers/char/hw_random/meson-rng.c
@@ -76,9 +76,6 @@ static int meson_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
struct meson_rng_data *data =
container_of(rng, struct meson_rng_data, rng);
- if (max < sizeof(u32))
- return 0;
-
*(u32 *)buf = readl_relaxed(data->base + RNG_DATA);
return sizeof(u32);
diff --git a/drivers/char/hw_random/st-rng.c b/drivers/char/hw_random/st-rng.c
index 1d35363..7e8aa6b 100644
--- a/drivers/char/hw_random/st-rng.c
+++ b/drivers/char/hw_random/st-rng.c
@@ -54,9 +54,6 @@ static int st_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
u32 status;
int i;
- if (max < sizeof(u16))
- return -EINVAL;
-
/* Wait until FIFO is full - max 4uS*/
for (i = 0; i < ST_RNG_FILL_FIFO_TIMEOUT; i++) {
status = readl_relaxed(ddata->base + ST_RNG_STATUS_REG);
--
2.5.0
^ permalink raw reply related
* [PATCH v2] crypto: caam - fix IV loading for authenc (giv)decryption
From: Horia Geantă @ 2016-08-26 15:17 UTC (permalink / raw)
To: Herbert Xu; +Cc: linux-crypto, David S. Miller
For algorithms that implement IV generators before the crypto ops,
the IV needed for decryption is initially located in req->src
scatterlist, not in req->iv.
Avoid copying the IV into req->iv by modifying the (givdecrypt)
descriptors to load it directly from req->src.
aead_givdecrypt() is no longer needed and goes away.
Cc: <stable@vger.kernel.org> # 4.3+
Fixes: 479bcc7c5b9e ("crypto: caam - Convert authenc to new AEAD interface")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
drivers/crypto/caam/caamalg.c | 77 +++++++++++++++++++++----------------------
1 file changed, 37 insertions(+), 40 deletions(-)
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 6dc597126b79..775b8b524913 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -556,7 +556,10 @@ skip_enc:
/* Read and write assoclen bytes */
append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+ if (alg->caam.geniv)
+ append_math_add_imm_u32(desc, VARSEQOUTLEN, REG3, IMM, ivsize);
+ else
+ append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
/* Skip assoc data */
append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
@@ -565,6 +568,14 @@ skip_enc:
append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
KEY_VLF);
+ if (alg->caam.geniv) {
+ append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
+ LDST_SRCDST_BYTE_CONTEXT |
+ (ctx1_iv_off << LDST_OFFSET_SHIFT));
+ append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO |
+ (ctx1_iv_off << MOVE_OFFSET_SHIFT) | ivsize);
+ }
+
/* Load Counter into CONTEXT1 reg */
if (is_rfc3686)
append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM |
@@ -2150,7 +2161,7 @@ static void init_authenc_job(struct aead_request *req,
init_aead_job(req, edesc, all_contig, encrypt);
- if (ivsize && (is_rfc3686 || !(alg->caam.geniv && encrypt)))
+ if (ivsize && !alg->caam.geniv)
append_load_as_imm(desc, req->iv, ivsize,
LDST_CLASS_1_CCB |
LDST_SRCDST_BYTE_CONTEXT |
@@ -2537,20 +2548,6 @@ static int aead_decrypt(struct aead_request *req)
return ret;
}
-static int aead_givdecrypt(struct aead_request *req)
-{
- struct crypto_aead *aead = crypto_aead_reqtfm(req);
- unsigned int ivsize = crypto_aead_ivsize(aead);
-
- if (req->cryptlen < ivsize)
- return -EINVAL;
-
- req->cryptlen -= ivsize;
- req->assoclen += ivsize;
-
- return aead_decrypt(req);
-}
-
/*
* allocate and map the ablkcipher extended descriptor for ablkcipher
*/
@@ -3210,7 +3207,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
},
@@ -3256,7 +3253,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
},
@@ -3302,7 +3299,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
},
@@ -3348,7 +3345,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
},
@@ -3394,7 +3391,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA384_DIGEST_SIZE,
},
@@ -3440,7 +3437,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA512_DIGEST_SIZE,
},
@@ -3486,7 +3483,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
},
@@ -3534,7 +3531,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
},
@@ -3582,7 +3579,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
},
@@ -3630,7 +3627,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
},
@@ -3678,7 +3675,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA384_DIGEST_SIZE,
},
@@ -3726,7 +3723,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA512_DIGEST_SIZE,
},
@@ -3772,7 +3769,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
},
@@ -3818,7 +3815,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
},
@@ -3864,7 +3861,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
},
@@ -3910,7 +3907,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
},
@@ -3956,7 +3953,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA384_DIGEST_SIZE,
},
@@ -4002,7 +3999,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA512_DIGEST_SIZE,
},
@@ -4051,7 +4048,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
},
@@ -4102,7 +4099,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
},
@@ -4153,7 +4150,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
},
@@ -4204,7 +4201,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
},
@@ -4255,7 +4252,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = SHA384_DIGEST_SIZE,
},
@@ -4306,7 +4303,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = SHA512_DIGEST_SIZE,
},
--
2.4.4
^ permalink raw reply related
* crypto: xor - Fix warning when XOR_SELECT_TEMPLATE is unset
From: Herbert Xu @ 2016-08-26 15:19 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Martin Schwidefsky, linux-next, linux-kernel,
Linux Crypto Mailing List
In-Reply-To: <20160825211411.08858397@canb.auug.org.au>
On Thu, Aug 25, 2016 at 09:14:11PM +1000, Stephen Rothwell wrote:
>
> That looks fine to me. An alternative might be to have:
>
> #ifndef XOR_SELECT_TEMPLATE
> #define XOR_SELECT_TEMPLATE(x) (x)
> #endif
>
> near the top of the file. That gets the #ifdef out of the code flow
> and serves as some hint that such a thing can be defined by arch header
> files.
Good idea. Thanks Stephen.
---8<---
This patch fixes an unused label warning triggered when the macro
XOR_SELECT_TEMPLATE is not set.
Fixes: 39457acda913 ("crypto: xor - skip speed test if the xor...")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Suggested-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
diff --git a/crypto/xor.c b/crypto/xor.c
index b8975d9..263af9f 100644
--- a/crypto/xor.c
+++ b/crypto/xor.c
@@ -24,6 +24,10 @@
#include <linux/preempt.h>
#include <asm/xor.h>
+#ifndef XOR_SELECT_TEMPLATE
+#define XOR_SELECT_TEMPLATE(x) (x)
+#endif
+
/* The xor routines to use. */
static struct xor_block_template *active_template;
@@ -109,17 +113,14 @@ calibrate_xor_blocks(void)
void *b1, *b2;
struct xor_block_template *f, *fastest;
- fastest = NULL;
+ fastest = XOR_SELECT_TEMPLATE(NULL);
-#ifdef XOR_SELECT_TEMPLATE
- fastest = XOR_SELECT_TEMPLATE(fastest);
if (fastest) {
printk(KERN_INFO "xor: automatically using best "
"checksumming function %-10s\n",
fastest->name);
goto out;
}
-#endif
/*
* Note: Since the memory is not actually used for _anything_ but to
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply related
* Re: [PATCH -next v2] chcr: Fix non static symbol warning
From: Herbert Xu @ 2016-08-26 14:42 UTC (permalink / raw)
To: Wei Yongjun
Cc: David S. Miller, Hariprasad Shenai, Atul Gupta, Wei Yongjun,
linux-crypto, netdev
In-Reply-To: <1472221268-25123-1-git-send-email-weiyj.lk@gmail.com>
On Fri, Aug 26, 2016 at 02:21:08PM +0000, Wei Yongjun wrote:
> From: Wei Yongjun <weiyongjun1@huawei.com>
>
> Fixes the following sparse warning:
>
> drivers/crypto/chelsio/chcr_algo.c:593:5: warning:
> symbol 'cxgb4_is_crypto_q_full' was not declared. Should it be static?
>
> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH] crypto: caam - fix IV loading for authenc (giv)decryption
From: Herbert Xu @ 2016-08-26 14:39 UTC (permalink / raw)
To: Horia Geantă; +Cc: linux-crypto, David S. Miller
In-Reply-To: <1472220822-18888-1-git-send-email-horia.geanta@nxp.com>
On Fri, Aug 26, 2016 at 05:13:42PM +0300, Horia Geantă wrote:
>
> In terms of optimizations, would it be safe to assume all "geniv" authenc
> algorithms - {echainiv, seqiv}(authenc) - get assoc,iv,ciphertext in
> req->src for decryption?
Yes. They all get the raw IPsec packet, apart from the ESN munging.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* [PATCH -next v2] chcr: Fix non static symbol warning
From: Wei Yongjun @ 2016-08-26 14:21 UTC (permalink / raw)
To: Herbert Xu, David S. Miller, Hariprasad Shenai, Atul Gupta
Cc: Wei Yongjun, linux-crypto, netdev
In-Reply-To: <1471882278-25777-1-git-send-email-weiyj.lk@gmail.com>
From: Wei Yongjun <weiyongjun1@huawei.com>
Fixes the following sparse warning:
drivers/crypto/chelsio/chcr_algo.c:593:5: warning:
symbol 'cxgb4_is_crypto_q_full' was not declared. Should it be static?
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
v1 -> v2: cc netdev maillist
---
drivers/crypto/chelsio/chcr_algo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c
index ad8e353..e4ddb92 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -590,7 +590,7 @@ badkey_err:
return -EINVAL;
}
-int cxgb4_is_crypto_q_full(struct net_device *dev, unsigned int idx)
+static int cxgb4_is_crypto_q_full(struct net_device *dev, unsigned int idx)
{
int ret = 0;
struct sge_ofld_txq *q;
^ permalink raw reply related
* [PATCH] crypto: caam - fix IV loading for authenc (giv)decryption
From: Horia Geantă @ 2016-08-26 14:13 UTC (permalink / raw)
To: Herbert Xu; +Cc: linux-crypto, David S. Miller
For algorithms that implement IV generators before the crypto ops,
the IV needed for decryption is initially located in req->src
scatterlist, not in req->iv.
aead_givdecrypt() is updated to put the IV in place.
Cc: <stable@vger.kernel.org> # 4.3+
Fixes: 479bcc7c5b9e ("crypto: caam - Convert authenc to new AEAD interface")
Suggested-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
Herbert, as you suggested, aead_givdecrypt() is now setting the IV.
In terms of optimizations, would it be safe to assume all "geniv" authenc
algorithms - {echainiv, seqiv}(authenc) - get assoc,iv,ciphertext in
req->src for decryption?
The idea would be to avoid copying IV into req->iv and instruct
the crypto engine to access it directly from req->src scatterlist.
drivers/crypto/caam/caamalg.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 6dc597126b79..78be2bea1273 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -2545,6 +2545,7 @@ static int aead_givdecrypt(struct aead_request *req)
if (req->cryptlen < ivsize)
return -EINVAL;
+ scatterwalk_map_and_copy(req->iv, req->src, req->assoclen, ivsize, 0);
req->cryptlen -= ivsize;
req->assoclen += ivsize;
--
2.4.4
^ permalink raw reply related
* Re: [PATCH v2 5/5] hwrng: amd: Rework of the amd768-hwrng driver
From: Jason Cooper @ 2016-08-26 13:29 UTC (permalink / raw)
To: LABBE Corentin; +Cc: mpm, herbert, linux-crypto, linux-kernel
In-Reply-To: <20160826083802.GA32290@Red>
Hi Corentin,
On Fri, Aug 26, 2016 at 10:38:02AM +0200, LABBE Corentin wrote:
> On Thu, Aug 25, 2016 at 02:56:38PM +0000, Jason Cooper wrote:
> > On Thu, Aug 25, 2016 at 02:16:35PM +0200, LABBE Corentin wrote:
> > > This patch convert the hwrng interface used by amd768-rng to its new API
> > > by replacing data_read()/data_present() by read().
> > >
> > > Furthermore, Instead of having two global variable, it's better to use a
> > > private struct. This will permit to remove amd_pdev variable.
> > >
> > > Finally, Instead of accessing hw directly via pmbase, it's better to
> > > access after ioport_map() via ioread32/iowrite32.
> >
> > I was going to recommend a better $subject line, but now I see why it's
> > vague. :( I would recommend breaking this patch up into three:
> >
> > hwrng: amd - Access hardware via ioread32/iowrite32
> > hwrng: amd - Replace global variable with private struct
> > hwrng: amd - Convert to new hwrng read() API
> >
>
> That was my first idea, but believed that it wasnt worth it.
When working with crypto/rng code, I'm a firm believer in moving
cautiously and deliberately. :-)
> Anyway I will do it.
Thanks!
thx,
Jason.
^ permalink raw reply
* Re: caam - IV source for IPsec decryption
From: Herbert Xu @ 2016-08-26 11:39 UTC (permalink / raw)
To: Horia Ioan Geanta Neag; +Cc: linux-crypto@vger.kernel.org
In-Reply-To: <DB4PR04MB0847411DA278511045969E6998ED0@DB4PR04MB0847.eurprd04.prod.outlook.com>
On Thu, Aug 25, 2016 at 04:12:35PM +0000, Horia Ioan Geanta Neag wrote:
> Herbert,
>
> Commits
> 7021b2e1cddd "esp4: Switch to new AEAD interface"
> 000ae7b2690e "esp6: Switch to new AEAD interface"
> removed the following:
> /* Get ivec. This can be wrong, check against another impls. */
> iv = esph->enc_data;
> from IPsec decryption - esp{4,6}_input(),
> so the IV in req->iv received by the implementer is no longer valid.
>
> Thus, the load of IV in caam driver - caamalg.c, init_authenc_job():
> if (ivsize && (is_rfc3686 || !(alg->caam.geniv && encrypt)))
> append_load_as_imm(desc, req->iv, ivsize,
> LDST_CLASS_1_CCB |
> LDST_SRCDST_BYTE_CONTEXT |
> (ivoffset << LDST_OFFSET_SHIFT));
> is not suited for case mentioned above.
>
> Instead, the IV should be read from the req->src scatterlist
> (which consists of assoc data, iv, ciphertext).
> Please let me know if this is accurate, so I could prepare a fix.
For authenc req->iv will be set by echainiv. But yes I seem to
have screwed this up for the echainiv ones in caam. You need to
change aead_givdecrypt to set req->iv.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* caam - IV source for IPsec decryption
From: Horia Ioan Geanta Neag @ 2016-08-26 7:40 UTC (permalink / raw)
To: Herbert Xu; +Cc: linux-crypto@vger.kernel.org
Herbert,
Commits
7021b2e1cddd "esp4: Switch to new AEAD interface"
000ae7b2690e "esp6: Switch to new AEAD interface"
removed the following:
/* Get ivec. This can be wrong, check against another impls. */
iv = esph->enc_data;
from IPsec decryption - esp{4,6}_input(),
so the IV in req->iv received by the implementer is no longer valid.
Thus, the load of IV in caam driver - caamalg.c, init_authenc_job():
if (ivsize && (is_rfc3686 || !(alg->caam.geniv && encrypt)))
append_load_as_imm(desc, req->iv, ivsize,
LDST_CLASS_1_CCB |
LDST_SRCDST_BYTE_CONTEXT |
(ivoffset << LDST_OFFSET_SHIFT));
is not suited for case mentioned above.
Instead, the IV should be read from the req->src scatterlist
(which consists of assoc data, iv, ciphertext).
Please let me know if this is accurate, so I could prepare a fix.
Thanks,
Horia
^ permalink raw reply
* [PATCH v3 0/8] hwrng: amd: rework of the amd hwrng driver
From: LABBE Corentin @ 2016-08-26 11:11 UTC (permalink / raw)
To: mpm, herbert, linux-crypto; +Cc: linux-kernel, LABBE Corentin
Changes since v2:
- split the latest patch in 4
Changes since v1:
- Keep the hwrng name as "amd"
LABBE Corentin (8):
hwrng: amd: Fix style problem with blank line
hwrng: amd: use the BIT macro
hwrng: amd: Be consitent with the driver name
hwrng: amd: Remove asm/io.h
hwrng: amd: release_region must be called after hwrng_unregister
hwrng: amd: Replace global variable with private struct
hwrng: amd: Access hardware via ioread32/iowrite32
hwrng: amd: Convert to new hwrng read() API
drivers/char/hw_random/amd-rng.c | 150 +++++++++++++++++++++++++--------------
1 file changed, 96 insertions(+), 54 deletions(-)
--
2.7.3
^ permalink raw reply
* [PATCH v3 8/8] hwrng: amd: Convert to new hwrng read() API
From: LABBE Corentin @ 2016-08-26 11:11 UTC (permalink / raw)
To: mpm, herbert, linux-crypto; +Cc: linux-kernel, LABBE Corentin
In-Reply-To: <1472209896-17197-1-git-send-email-clabbe.montjoie@gmail.com>
This patch convert the hwrng interface used by amd768-rng to its new API
by replacing data_read()/data_present() by read().
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
---
drivers/char/hw_random/amd-rng.c | 47 ++++++++++++++++++++++++----------------
1 file changed, 28 insertions(+), 19 deletions(-)
diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c
index bfa14b9..9959c76 100644
--- a/drivers/char/hw_random/amd-rng.c
+++ b/drivers/char/hw_random/amd-rng.c
@@ -58,27 +58,37 @@ struct amd768_priv {
u32 pmbase;
};
-static int amd_rng_data_present(struct hwrng *rng, int wait)
+static int amd_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
+ u32 *data = buf;
struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
- int data, i;
-
- for (i = 0; i < 20; i++) {
- data = !!(ioread32(priv->iobase + RNGDONE) & 1);
- if (data || !wait)
- break;
- udelay(10);
+ size_t read = 0;
+ /* We will wait at maximum one time per read */
+ int timeout = max / 4 + 1;
+
+ /*
+ * RNG data is available when RNGDONE is set to 1
+ * New random numbers are generated approximately 128 microseconds
+ * after RNGDATA is read
+ */
+ while (read < max) {
+ if (ioread32(priv->iobase + RNGDONE) == 0) {
+ if (wait) {
+ /* Delay given by datasheet */
+ usleep_range(128, 196);
+ if (timeout-- == 0)
+ return read;
+ } else {
+ return 0;
+ }
+ } else {
+ *data = ioread32(priv->iobase + RNGDATA);
+ data++;
+ read += 4;
+ }
}
- return data;
-}
-
-static int amd_rng_data_read(struct hwrng *rng, u32 *data)
-{
- struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
-
- *data = ioread32(priv->iobase + RNGDATA);
- return 4;
+ return read;
}
static int amd_rng_init(struct hwrng *rng)
@@ -111,8 +121,7 @@ static struct hwrng amd_rng = {
.name = "amd",
.init = amd_rng_init,
.cleanup = amd_rng_cleanup,
- .data_present = amd_rng_data_present,
- .data_read = amd_rng_data_read,
+ .read = amd_rng_read,
};
static int __init mod_init(void)
--
2.7.3
^ permalink raw reply related
* [PATCH v3 7/8] hwrng: amd: Access hardware via ioread32/iowrite32
From: LABBE Corentin @ 2016-08-26 11:11 UTC (permalink / raw)
To: mpm, herbert, linux-crypto; +Cc: linux-kernel, LABBE Corentin
In-Reply-To: <1472209896-17197-1-git-send-email-clabbe.montjoie@gmail.com>
Instead of accessing hw directly via pmbase, it's better to
access after ioport_map() via ioread32/iowrite32.
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
---
drivers/char/hw_random/amd-rng.c | 31 +++++++++++++++++++++++++------
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c
index 4ef94e9..bfa14b9 100644
--- a/drivers/char/hw_random/amd-rng.c
+++ b/drivers/char/hw_random/amd-rng.c
@@ -32,6 +32,11 @@
#define DRV_NAME "AMD768-HWRNG"
+#define RNGDATA 0x00
+#define RNGDONE 0x04
+#define PMBASE_OFFSET 0xF0
+#define PMBASE_SIZE 8
+
/*
* Data for PCI driver interface
*
@@ -48,6 +53,7 @@ static const struct pci_device_id pci_tbl[] = {
MODULE_DEVICE_TABLE(pci, pci_tbl);
struct amd768_priv {
+ void __iomem *iobase;
struct pci_dev *pcidev;
u32 pmbase;
};
@@ -58,7 +64,7 @@ static int amd_rng_data_present(struct hwrng *rng, int wait)
int data, i;
for (i = 0; i < 20; i++) {
- data = !!(inl(priv->pmbase + 0xF4) & 1);
+ data = !!(ioread32(priv->iobase + RNGDONE) & 1);
if (data || !wait)
break;
udelay(10);
@@ -70,7 +76,7 @@ static int amd_rng_data_read(struct hwrng *rng, u32 *data)
{
struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
- *data = inl(priv->pmbase + 0xF0);
+ *data = ioread32(priv->iobase + RNGDATA);
return 4;
}
@@ -138,12 +144,20 @@ found:
if (!priv)
return -ENOMEM;
- if (!request_region(pmbase + 0xF0, 8, DRV_NAME)) {
+ if (!request_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE, DRV_NAME)) {
dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
pmbase + 0xF0);
err = -EBUSY;
goto out;
}
+
+ priv->iobase = ioport_map(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
+ if (!priv->iobase) {
+ pr_err(DRV_NAME "Cannot map ioport\n");
+ err = -EINVAL;
+ goto err_iomap;
+ }
+
amd_rng.priv = (unsigned long)priv;
priv->pmbase = pmbase;
priv->pcidev = pdev;
@@ -152,11 +166,14 @@ found:
err = hwrng_register(&amd_rng);
if (err) {
pr_err(DRV_NAME " registering failed (%d)\n", err);
- release_region(pmbase + 0xF0, 8);
- goto out;
+ goto err_hwrng;
}
return 0;
+err_hwrng:
+ ioport_unmap(priv->iobase);
+err_iomap:
+ release_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
out:
kfree(priv);
return err;
@@ -170,7 +187,9 @@ static void __exit mod_exit(void)
hwrng_unregister(&amd_rng);
- release_region(priv->pmbase + 0xF0, 8);
+ ioport_unmap(priv->iobase);
+
+ release_region(priv->pmbase + PMBASE_OFFSET, PMBASE_SIZE);
kfree(priv);
}
--
2.7.3
^ permalink raw reply related
* [PATCH v3 6/8] hwrng: amd: Replace global variable with private struct
From: LABBE Corentin @ 2016-08-26 11:11 UTC (permalink / raw)
To: mpm, herbert, linux-crypto; +Cc: linux-kernel, LABBE Corentin
In-Reply-To: <1472209896-17197-1-git-send-email-clabbe.montjoie@gmail.com>
Instead of having two global variable, it's better to use a
private struct. This will permit to remove amd_pdev variable
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
---
drivers/char/hw_random/amd-rng.c | 57 ++++++++++++++++++++++++++--------------
1 file changed, 38 insertions(+), 19 deletions(-)
diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c
index 383e197..4ef94e9 100644
--- a/drivers/char/hw_random/amd-rng.c
+++ b/drivers/char/hw_random/amd-rng.c
@@ -47,15 +47,18 @@ static const struct pci_device_id pci_tbl[] = {
};
MODULE_DEVICE_TABLE(pci, pci_tbl);
-static struct pci_dev *amd_pdev;
+struct amd768_priv {
+ struct pci_dev *pcidev;
+ u32 pmbase;
+};
static int amd_rng_data_present(struct hwrng *rng, int wait)
{
- u32 pmbase = (u32)rng->priv;
+ struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
int data, i;
for (i = 0; i < 20; i++) {
- data = !!(inl(pmbase + 0xF4) & 1);
+ data = !!(inl(priv->pmbase + 0xF4) & 1);
if (data || !wait)
break;
udelay(10);
@@ -65,35 +68,37 @@ static int amd_rng_data_present(struct hwrng *rng, int wait)
static int amd_rng_data_read(struct hwrng *rng, u32 *data)
{
- u32 pmbase = (u32)rng->priv;
+ struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
- *data = inl(pmbase + 0xF0);
+ *data = inl(priv->pmbase + 0xF0);
return 4;
}
static int amd_rng_init(struct hwrng *rng)
{
+ struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
u8 rnen;
- pci_read_config_byte(amd_pdev, 0x40, &rnen);
+ pci_read_config_byte(priv->pcidev, 0x40, &rnen);
rnen |= BIT(7); /* RNG on */
- pci_write_config_byte(amd_pdev, 0x40, rnen);
+ pci_write_config_byte(priv->pcidev, 0x40, rnen);
- pci_read_config_byte(amd_pdev, 0x41, &rnen);
+ pci_read_config_byte(priv->pcidev, 0x41, &rnen);
rnen |= BIT(7); /* PMIO enable */
- pci_write_config_byte(amd_pdev, 0x41, rnen);
+ pci_write_config_byte(priv->pcidev, 0x41, rnen);
return 0;
}
static void amd_rng_cleanup(struct hwrng *rng)
{
+ struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
u8 rnen;
- pci_read_config_byte(amd_pdev, 0x40, &rnen);
+ pci_read_config_byte(priv->pcidev, 0x40, &rnen);
rnen &= ~BIT(7); /* RNG off */
- pci_write_config_byte(amd_pdev, 0x40, rnen);
+ pci_write_config_byte(priv->pcidev, 0x40, rnen);
}
static struct hwrng amd_rng = {
@@ -110,6 +115,7 @@ static int __init mod_init(void)
struct pci_dev *pdev = NULL;
const struct pci_device_id *ent;
u32 pmbase;
+ struct amd768_priv *priv;
for_each_pci_dev(pdev) {
ent = pci_match_id(pci_tbl, pdev);
@@ -117,24 +123,30 @@ static int __init mod_init(void)
goto found;
}
/* Device not found. */
- goto out;
+ return -ENODEV;
found:
err = pci_read_config_dword(pdev, 0x58, &pmbase);
if (err)
- goto out;
- err = -EIO;
+ return err;
+
pmbase &= 0x0000FF00;
if (pmbase == 0)
- goto out;
+ return -EIO;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
if (!request_region(pmbase + 0xF0, 8, DRV_NAME)) {
dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
pmbase + 0xF0);
err = -EBUSY;
goto out;
}
- amd_rng.priv = (unsigned long)pmbase;
- amd_pdev = pdev;
+ amd_rng.priv = (unsigned long)priv;
+ priv->pmbase = pmbase;
+ priv->pcidev = pdev;
pr_info(DRV_NAME " detected\n");
err = hwrng_register(&amd_rng);
@@ -143,17 +155,24 @@ found:
release_region(pmbase + 0xF0, 8);
goto out;
}
+ return 0;
+
out:
+ kfree(priv);
return err;
}
static void __exit mod_exit(void)
{
- u32 pmbase = (unsigned long)amd_rng.priv;
+ struct amd768_priv *priv;
+
+ priv = (struct amd768_priv *)amd_rng.priv;
hwrng_unregister(&amd_rng);
- release_region(pmbase + 0xF0, 8);
+ release_region(priv->pmbase + 0xF0, 8);
+
+ kfree(priv);
}
module_init(mod_init);
--
2.7.3
^ permalink raw reply related
* [PATCH v3 5/8] hwrng: amd: release_region must be called after hwrng_unregister
From: LABBE Corentin @ 2016-08-26 11:11 UTC (permalink / raw)
To: mpm, herbert, linux-crypto; +Cc: linux-kernel, LABBE Corentin
In-Reply-To: <1472209896-17197-1-git-send-email-clabbe.montjoie@gmail.com>
The driver release the memory region before being sure that nobody use
it.
This patch made hwrng_unregister ran before any release was done.
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
---
drivers/char/hw_random/amd-rng.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c
index de82fe3..383e197 100644
--- a/drivers/char/hw_random/amd-rng.c
+++ b/drivers/char/hw_random/amd-rng.c
@@ -151,8 +151,9 @@ static void __exit mod_exit(void)
{
u32 pmbase = (unsigned long)amd_rng.priv;
- release_region(pmbase + 0xF0, 8);
hwrng_unregister(&amd_rng);
+
+ release_region(pmbase + 0xF0, 8);
}
module_init(mod_init);
--
2.7.3
^ permalink raw reply related
* [PATCH v3 4/8] hwrng: amd: Remove asm/io.h
From: LABBE Corentin @ 2016-08-26 11:11 UTC (permalink / raw)
To: mpm, herbert, linux-crypto; +Cc: linux-kernel, LABBE Corentin
In-Reply-To: <1472209896-17197-1-git-send-email-clabbe.montjoie@gmail.com>
checkpatch complains about <asm/io.h> used instead of linux/io.h.
In fact it is not needed.
This patch remove it, and in the process, alphabetize the other headers.
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
---
drivers/char/hw_random/amd-rng.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c
index 93157af..de82fe3 100644
--- a/drivers/char/hw_random/amd-rng.c
+++ b/drivers/char/hw_random/amd-rng.c
@@ -24,12 +24,11 @@
* warranty of any kind, whether express or implied.
*/
-#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/hw_random.h>
#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/pci.h>
-#include <linux/hw_random.h>
-#include <linux/delay.h>
-#include <asm/io.h>
#define DRV_NAME "AMD768-HWRNG"
--
2.7.3
^ permalink raw reply related
* [PATCH v3 3/8] hwrng: amd: Be consitent with the driver name
From: LABBE Corentin @ 2016-08-26 11:11 UTC (permalink / raw)
To: mpm, herbert, linux-crypto; +Cc: linux-kernel, LABBE Corentin
In-Reply-To: <1472209896-17197-1-git-send-email-clabbe.montjoie@gmail.com>
The driver name is displayed each time differently.
This patch make use of the same name everywhere.
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
---
drivers/char/hw_random/amd-rng.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c
index d0042f5..93157af 100644
--- a/drivers/char/hw_random/amd-rng.c
+++ b/drivers/char/hw_random/amd-rng.c
@@ -31,7 +31,7 @@
#include <linux/delay.h>
#include <asm/io.h>
-#define PFX KBUILD_MODNAME ": "
+#define DRV_NAME "AMD768-HWRNG"
/*
* Data for PCI driver interface
@@ -128,8 +128,8 @@ found:
pmbase &= 0x0000FF00;
if (pmbase == 0)
goto out;
- if (!request_region(pmbase + 0xF0, 8, "AMD HWRNG")) {
- dev_err(&pdev->dev, "AMD HWRNG region 0x%x already in use!\n",
+ if (!request_region(pmbase + 0xF0, 8, DRV_NAME)) {
+ dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
pmbase + 0xF0);
err = -EBUSY;
goto out;
@@ -137,11 +137,10 @@ found:
amd_rng.priv = (unsigned long)pmbase;
amd_pdev = pdev;
- pr_info("AMD768 RNG detected\n");
+ pr_info(DRV_NAME " detected\n");
err = hwrng_register(&amd_rng);
if (err) {
- pr_err(PFX "RNG registering failed (%d)\n",
- err);
+ pr_err(DRV_NAME " registering failed (%d)\n", err);
release_region(pmbase + 0xF0, 8);
goto out;
}
--
2.7.3
^ permalink raw reply related
* [PATCH v3 2/8] hwrng: amd: use the BIT macro
From: LABBE Corentin @ 2016-08-26 11:11 UTC (permalink / raw)
To: mpm, herbert, linux-crypto; +Cc: linux-kernel, LABBE Corentin
In-Reply-To: <1472209896-17197-1-git-send-email-clabbe.montjoie@gmail.com>
This patch add usage of the BIT() macro
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
---
drivers/char/hw_random/amd-rng.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c
index 45b7965..d0042f5 100644
--- a/drivers/char/hw_random/amd-rng.c
+++ b/drivers/char/hw_random/amd-rng.c
@@ -78,11 +78,11 @@ static int amd_rng_init(struct hwrng *rng)
u8 rnen;
pci_read_config_byte(amd_pdev, 0x40, &rnen);
- rnen |= (1 << 7); /* RNG on */
+ rnen |= BIT(7); /* RNG on */
pci_write_config_byte(amd_pdev, 0x40, rnen);
pci_read_config_byte(amd_pdev, 0x41, &rnen);
- rnen |= (1 << 7); /* PMIO enable */
+ rnen |= BIT(7); /* PMIO enable */
pci_write_config_byte(amd_pdev, 0x41, rnen);
return 0;
@@ -93,7 +93,7 @@ static void amd_rng_cleanup(struct hwrng *rng)
u8 rnen;
pci_read_config_byte(amd_pdev, 0x40, &rnen);
- rnen &= ~(1 << 7); /* RNG off */
+ rnen &= ~BIT(7); /* RNG off */
pci_write_config_byte(amd_pdev, 0x40, rnen);
}
--
2.7.3
^ permalink raw reply related
* [PATCH v3 1/8] hwrng: amd: Fix style problem with blank line
From: LABBE Corentin @ 2016-08-26 11:11 UTC (permalink / raw)
To: mpm, herbert, linux-crypto; +Cc: linux-kernel, LABBE Corentin
In-Reply-To: <1472209896-17197-1-git-send-email-clabbe.montjoie@gmail.com>
Some blank line are unncessary, and one is missing after declaration.
This patch fix thoses style problems.
Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
---
drivers/char/hw_random/amd-rng.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c
index 48f6a83..45b7965 100644
--- a/drivers/char/hw_random/amd-rng.c
+++ b/drivers/char/hw_random/amd-rng.c
@@ -31,10 +31,8 @@
#include <linux/delay.h>
#include <asm/io.h>
-
#define PFX KBUILD_MODNAME ": "
-
/*
* Data for PCI driver interface
*
@@ -52,7 +50,6 @@ MODULE_DEVICE_TABLE(pci, pci_tbl);
static struct pci_dev *amd_pdev;
-
static int amd_rng_data_present(struct hwrng *rng, int wait)
{
u32 pmbase = (u32)rng->priv;
@@ -100,7 +97,6 @@ static void amd_rng_cleanup(struct hwrng *rng)
pci_write_config_byte(amd_pdev, 0x40, rnen);
}
-
static struct hwrng amd_rng = {
.name = "amd",
.init = amd_rng_init,
@@ -109,7 +105,6 @@ static struct hwrng amd_rng = {
.data_read = amd_rng_data_read,
};
-
static int __init mod_init(void)
{
int err = -ENODEV;
@@ -157,6 +152,7 @@ out:
static void __exit mod_exit(void)
{
u32 pmbase = (unsigned long)amd_rng.priv;
+
release_region(pmbase + 0xF0, 8);
hwrng_unregister(&amd_rng);
}
--
2.7.3
^ permalink raw reply related
* [PATCH] fix:caam:ctrl:add missing header dependencies
From: Baoyou Xie @ 2016-08-26 9:56 UTC (permalink / raw)
To: herbert, davem
Cc: arnd, baoyou.xie, tudor-dan.ambarus, linux-crypto, linux-kernel,
xie.baoyou
We get 1 warning when biuld kernel with W=1:
drivers/crypto/caam/ctrl.c:398:5: warning: no previous prototype for 'caam_get_era' [-Wmissing-prototypes]
In fact, this function is declared in drivers/crypto/caam/ctrl.h,
so this patch add missing header dependencies.
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
---
drivers/crypto/caam/ctrl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 0ec112e..46e72ed 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -14,6 +14,7 @@
#include "jr.h"
#include "desc_constr.h"
#include "error.h"
+#include "ctrl.h"
bool caam_little_end;
EXPORT_SYMBOL(caam_little_end);
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v2 5/5] hwrng: amd: Rework of the amd768-hwrng driver
From: LABBE Corentin @ 2016-08-26 8:38 UTC (permalink / raw)
To: Jason Cooper; +Cc: mpm, herbert, linux-crypto, linux-kernel
In-Reply-To: <20160825145638.GD10637@io.lakedaemon.net>
On Thu, Aug 25, 2016 at 02:56:38PM +0000, Jason Cooper wrote:
> Hi Corentin,
>
> On Thu, Aug 25, 2016 at 02:16:35PM +0200, LABBE Corentin wrote:
> > This patch convert the hwrng interface used by amd768-rng to its new API
> > by replacing data_read()/data_present() by read().
> >
> > Furthermore, Instead of having two global variable, it's better to use a
> > private struct. This will permit to remove amd_pdev variable.
> >
> > Finally, Instead of accessing hw directly via pmbase, it's better to
> > access after ioport_map() via ioread32/iowrite32.
>
> I was going to recommend a better $subject line, but now I see why it's
> vague. :( I would recommend breaking this patch up into three:
>
> hwrng: amd - Access hardware via ioread32/iowrite32
> hwrng: amd - Replace global variable with private struct
> hwrng: amd - Convert to new hwrng read() API
>
That was my first idea, but believed that it wasnt worth it.
Anyway I will do it.
Regards
LABBE Corentin
^ permalink raw reply
* sha1_mb broken
From: Stephan Mueller @ 2016-08-26 1:15 UTC (permalink / raw)
To: linux-crypto
Hi,
I tried to execute tests with sha1_mb.
The execution simply stalls when invoking a digest operation -- i.e. the
digest operation does not finish. After some time after invoking the hashing
operation, the following log appears (note, the kccavs_* functions are my test
code; that test code works perfectly well with all other hash
implementations):
[ 140.426026] INFO: rcu_sched detected stalls on CPUs/tasks:
[ 140.426719] 2-...: (1 GPs behind) idle=9c3/140000000000000/0
softirq=2680/2707 fqs=14762
[ 140.427024] (detected by 0, t=60002 jiffies, g=655, c=654, q=35)
[ 140.427024] Task dump for CPU 2:
[ 140.427024] cavs_driver R running task 0 945 862
0x00000008
[ 140.427024] ffffffff9b78d965 ffffa527b8bfa640 ffffa527bb505940
ffffa52775c20c50
[ 140.427024] ffffa527bc300000 ffffa527b93d2a80 ffffa527bb857e00
ffffa527bc2ffd78
[ 140.427024] ffffa527b93d2ac8 ffffa527bc2ffcc0 ffffffff9b78dfc8
ffffa527bc2ffd70
[ 140.427024] Call Trace:
[ 140.427024] [<ffffffff9b78d965>] ? __schedule+0x245/0x690
[ 140.427024] [<ffffffff9b78dfc8>] ? preempt_schedule_common+0x18/0x30
[ 140.427024] [<ffffffff9b791a68>] ? _raw_spin_lock_irq+0x28/0x30
[ 140.427024] [<ffffffff9b78ed98>] ? wait_for_completion_interruptible
+0x28/0x180
[ 140.427024] [<ffffffffc028541c>] ? sha1_mb_async_digest+0x6c/0x70
[sha1_mb]
[ 140.427024] [<ffffffff9b3b1129>] ? crypto_ahash_op+0x29/0x70
[ 140.427024] [<ffffffffc0270148>] ? kccavs_test_ahash+0x198/0x2b0
[kcapi_cavs]
[ 140.427024] [<ffffffffc026e20a>] ? kccavs_data_read+0xda/0x160
[kcapi_cavs]
[ 140.427024] [<ffffffff9b370964>] ? full_proxy_read+0x54/0x90
[ 140.427024] [<ffffffff9b208088>] ? __vfs_read+0x28/0x110
[ 140.427024] [<ffffffff9b38a2c0>] ? security_file_permission+0xa0/0xc0
[ 140.427024] [<ffffffff9b20850e>] ? rw_verify_area+0x4e/0xb0
[ 140.427024] [<ffffffff9b208606>] ? vfs_read+0x96/0x130
[ 140.427024] [<ffffffff9b2099f6>] ? SyS_read+0x46/0xa0
[ 140.427024] [<ffffffff9b791cb6>] ? entry_SYSCALL_64_fastpath+0x1e/0xa8
Ciao
Stephan
^ permalink raw reply
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