* Re: [PATCH v2] crypto: caam - fix IV loading for authenc (giv)decryption
From: Horia Ioan Geanta Neag @ 2016-08-29 9:58 UTC (permalink / raw)
To: Herbert Xu; +Cc: linux-crypto@vger.kernel.org, David S. Miller
In-Reply-To: <1472224633-25412-1-git-send-email-horia.geanta@nxp.com>
On 8/26/2016 6:33 PM, Horia Geantă wrote:
> For algorithms that implement IV generators before the crypto ops,
> the IV needed for decryption is initially located in req->src
> scatterlist, not in req->iv.
>
> Avoid copying the IV into req->iv by modifying the (givdecrypt)
> descriptors to load it directly from req->src.
> aead_givdecrypt() is no longer needed and goes away.
>
> Cc: <stable@vger.kernel.org> # 4.3+
> Fixes: 479bcc7c5b9e ("crypto: caam - Convert authenc to new AEAD interface")
> Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
> ---
>
> drivers/crypto/caam/caamalg.c | 77 +++++++++++++++++++++----------------------
> 1 file changed, 37 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
> index 6dc597126b79..775b8b524913 100644
> --- a/drivers/crypto/caam/caamalg.c
> +++ b/drivers/crypto/caam/caamalg.c
> @@ -556,7 +556,10 @@ skip_enc:
>
> /* Read and write assoclen bytes */
> append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
> - append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
> + if (alg->caam.geniv)
> + append_math_add_imm_u32(desc, VARSEQOUTLEN, REG3, IMM, ivsize);
> + else
> + append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
>
> /* Skip assoc data */
> append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
> @@ -565,6 +568,14 @@ skip_enc:
> append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
> KEY_VLF);
>
> + if (alg->caam.geniv) {
> + append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
> + LDST_SRCDST_BYTE_CONTEXT |
> + (ctx1_iv_off << LDST_OFFSET_SHIFT));
> + append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO |
> + (ctx1_iv_off << MOVE_OFFSET_SHIFT) | ivsize);
> + }
> +
> /* Load Counter into CONTEXT1 reg */
> if (is_rfc3686)
> append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM |
> @@ -2150,7 +2161,7 @@ static void init_authenc_job(struct aead_request *req,
>
> init_aead_job(req, edesc, all_contig, encrypt);
>
> - if (ivsize && (is_rfc3686 || !(alg->caam.geniv && encrypt)))
> + if (ivsize && !alg->caam.geniv)
This condition update is incorrect, since IV won't be loaded neither
here nor in the givencrypt aead descriptor for rfc3686 case.
I'll send v3 shortly.
> append_load_as_imm(desc, req->iv, ivsize,
> LDST_CLASS_1_CCB |
> LDST_SRCDST_BYTE_CONTEXT |
^ permalink raw reply
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From: 罗蒯高 @ 2016-08-29 5:05 UTC (permalink / raw)
To: linux-crypto
From: 罗蒯高
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^ permalink raw reply
* Re: [PATCH v2 3/4] hw_random: jz4780-rng: Add RNG node to jz4780.dtsi
From: PrasannaKumar Muralidharan @ 2016-08-28 17:59 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: mpm, Herbert Xu, robh+dt, mark.rutland, Ralf Baechle, Greg KH,
boris.brezillon, harvey.hunt, prarit, Florian Fainelli,
joshua.henderson, narmstrong, Linus Walleij, linux-crypto,
devicetree, linux-mips
In-Reply-To: <7a3874e2-069e-7bdf-2289-3364ec2c8cc4@cogentembedded.com>
>> cgu: jz4780-cgu@10000000 {
>> compatible = "ingenic,jz4780-cgu";
>> - reg = <0x10000000 0x100>;
>> + reg = <0x10000000 0xD8>;
>
>
> I think lower case is preferred here.
Sure, will change.
^ permalink raw reply
* Re: [PATCH v2 3/4] hw_random: jz4780-rng: Add RNG node to jz4780.dtsi
From: Sergei Shtylyov @ 2016-08-28 10:33 UTC (permalink / raw)
To: PrasannaKumar Muralidharan, mpm-VDJrAJ4Gl5ZBDgjK7y7TUQ,
herbert-lOAM2aK0SrRLBo1qDEOMRrpzq4S04n8Q,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
ralf-6z/3iImG2C8G8FEW9MqTrA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
harvey.hunt-1AXoQHu6uovQT0dZR+AlfA, prarit-H+wXaHxf7aLQT0dZR+AlfA,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w,
joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA,
narmstrong-rdvid1DuHRBWk0Htik3J/w,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linux-crypto-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA
In-Reply-To: <1472321697-3094-4-git-send-email-prasannatsmkumar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hello.
On 8/27/2016 9:14 PM, PrasannaKumar Muralidharan wrote:
> This patch adds RNG node to jz4780.dtsi.
>
> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/mips/boot/dts/ingenic/jz4780.dtsi | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> index b868b42..f11d139 100644
> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> @@ -36,7 +36,7 @@
>
> cgu: jz4780-cgu@10000000 {
> compatible = "ingenic,jz4780-cgu";
> - reg = <0x10000000 0x100>;
> + reg = <0x10000000 0xD8>;
I think lower case is preferred here.
>
> clocks = <&ext>, <&rtc>;
> clock-names = "ext", "rtc";
> @@ -44,6 +44,11 @@
> #clock-cells = <1>;
> };
>
> + rng: jz4780-rng@100000D8 {
All in lower case, please.
> + compatible = "ingenic,jz4780-rng";
> + reg = <0x100000D8 0x8>;
Likewise.
[...]
MBR, Sergei
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^ permalink raw reply
* [PATCH] Use devm_hwrng_register instead of hwrng_register
From: PrasannaKumar Muralidharan @ 2016-08-28 8:49 UTC (permalink / raw)
To: mpm, herbert, linux-crypto; +Cc: PrasannaKumar Muralidharan
By using devm_hwrng_register instead of hwrng_register the .remove
callback in platform_driver can be removed. This reduces a few lines in
code.
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
drivers/char/hw_random/tx4939-rng.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/char/hw_random/tx4939-rng.c b/drivers/char/hw_random/tx4939-rng.c
index a7b6949..1093583 100644
--- a/drivers/char/hw_random/tx4939-rng.c
+++ b/drivers/char/hw_random/tx4939-rng.c
@@ -144,22 +144,13 @@ static int __init tx4939_rng_probe(struct platform_device *dev)
}
platform_set_drvdata(dev, rngdev);
- return hwrng_register(&rngdev->rng);
-}
-
-static int __exit tx4939_rng_remove(struct platform_device *dev)
-{
- struct tx4939_rng *rngdev = platform_get_drvdata(dev);
-
- hwrng_unregister(&rngdev->rng);
- return 0;
+ return devm_hwrng_register(&dev->dev, &rngdev->rng);
}
static struct platform_driver tx4939_rng_driver = {
.driver = {
.name = "tx4939-rng",
},
- .remove = tx4939_rng_remove,
};
module_platform_driver_probe(tx4939_rng_driver, tx4939_rng_probe);
--
2.5.0
^ permalink raw reply related
* [PATCH v2 3/4] hw_random: jz4780-rng: Add RNG node to jz4780.dtsi
From: PrasannaKumar Muralidharan @ 2016-08-27 18:14 UTC (permalink / raw)
To: mpm, herbert, robh+dt, mark.rutland, ralf, gregkh,
boris.brezillon, harvey.hunt, prarit, f.fainelli,
joshua.henderson, narmstrong, linus.walleij, linux-crypto,
devicetree, linux-mips
Cc: PrasannaKumar Muralidharan
In-Reply-To: <1472321697-3094-1-git-send-email-prasannatsmkumar@gmail.com>
This patch adds RNG node to jz4780.dtsi.
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index b868b42..f11d139 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -36,7 +36,7 @@
cgu: jz4780-cgu@10000000 {
compatible = "ingenic,jz4780-cgu";
- reg = <0x10000000 0x100>;
+ reg = <0x10000000 0xD8>;
clocks = <&ext>, <&rtc>;
clock-names = "ext", "rtc";
@@ -44,6 +44,11 @@
#clock-cells = <1>;
};
+ rng: jz4780-rng@100000D8 {
+ compatible = "ingenic,jz4780-rng";
+ reg = <0x100000D8 0x8>;
+ };
+
uart0: serial@10030000 {
compatible = "ingenic,jz4780-uart";
reg = <0x10030000 0x100>;
--
2.5.0
^ permalink raw reply related
* [PATCH v2 2/4] hw_random: jz4780-rng: Add Ingenic JZ4780 hardware RNG driver
From: PrasannaKumar Muralidharan @ 2016-08-27 18:14 UTC (permalink / raw)
To: mpm, herbert, robh+dt, mark.rutland, ralf, gregkh,
boris.brezillon, harvey.hunt, prarit, f.fainelli,
joshua.henderson, narmstrong, linus.walleij, linux-crypto,
devicetree, linux-mips
Cc: PrasannaKumar Muralidharan
In-Reply-To: <1472321697-3094-1-git-send-email-prasannatsmkumar@gmail.com>
JZ4780 SoC random number generator driver.
Changes since v1:
* Use devm_ioremap_resource and devm_hwrng_register
* Add delay after enabling RNG, before reading data
* Disable RNG after reading data as per Ingenic JZ4780 PM
* Move Makefile and Kconfig entries to the bottom
* Arrange includes in alphabetical order
Adding a delay before reading RNG data and disabling RNG after reading
data was suggested by Jeffery Walton.
Suggested-by: Jeffrey Walton <noloader@gmail.com>
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
MAINTAINERS | 5 ++
drivers/char/hw_random/Kconfig | 14 +++++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/jz4780-rng.c | 101 ++++++++++++++++++++++++++++++++++++
4 files changed, 121 insertions(+)
create mode 100644 drivers/char/hw_random/jz4780-rng.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 320cce8..87a7505 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6008,6 +6008,11 @@ M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
S: Maintained
F: drivers/dma/dma-jz4780.c
+INGENIC JZ4780 HW RNG Driver
+M: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+S: Maintained
+F: drivers/char/hw_random/jz4780-rng.c
+
INTEGRITY MEASUREMENT ARCHITECTURE (IMA)
M: Mimi Zohar <zohar@linux.vnet.ibm.com>
M: Dmitry Kasatkin <dmitry.kasatkin@gmail.com>
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 56ad5a59..662e415 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -410,6 +410,20 @@ config HW_RANDOM_MESON
If unsure, say Y.
+config HW_RANDOM_JZ4780
+ tristate "JZ4780 HW random number generator support"
+ depends on MACH_INGENIC
+ depends on HAS_IOMEM
+ default HW_RANDOM
+ ---help---
+ This driver provides kernel-side support for the Random Number
+ Generator hardware found on JZ4780 SOCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called jz4780-rng.
+
+ If unsure, say Y.
+
endif # HW_RANDOM
config UML_RANDOM
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 04bb0b0..df1dbf6 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -35,3 +35,4 @@ obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
+obj-$(CONFIG_HW_RANDOM_JZ4780) += jz4780-rng.o
diff --git a/drivers/char/hw_random/jz4780-rng.c b/drivers/char/hw_random/jz4780-rng.c
new file mode 100644
index 0000000..1c85ed0
--- /dev/null
+++ b/drivers/char/hw_random/jz4780-rng.c
@@ -0,0 +1,101 @@
+/*
+ * jz4780-rng.c - Random Number Generator driver for J4780
+ *
+ * Copyright 2016 (C) PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/hw_random.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#define REG_RNG_CTRL 0x0
+#define REG_RNG_DATA 0x4
+
+struct jz4780_rng {
+ struct device *dev;
+ struct hwrng rng;
+ void __iomem *mem;
+};
+
+static u32 jz4780_rng_readl(struct jz4780_rng *rng, u32 offset)
+{
+ return readl(rng->mem + offset);
+}
+
+static void jz4780_rng_writel(struct jz4780_rng *rng, u32 val, u32 offset)
+{
+ writel(val, rng->mem + offset);
+}
+
+static int jz4780_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+ struct jz4780_rng *jz4780_rng = container_of(rng, struct jz4780_rng,
+ rng);
+ u32 *data = buf;
+ /*
+ * JZ4780 Programmers manual says the RNG should not run continuously
+ * for more than 1s. So enable RNG, read data and disable it.
+ * NOTE: No issue was observed with MIPS creator CI20 board even when
+ * RNG ran continuously for longer periods. This is just a precaution.
+ *
+ * A delay is required so that the current RNG data is not bit shifted
+ * version of previous RNG data which could happen if random data is
+ * read continuously from this device.
+ */
+ jz4780_rng_writel(jz4780_rng, 1, REG_RNG_CTRL);
+ /* As the delay is small add it even if wait is false */
+ udelay(20);
+ *data = jz4780_rng_readl(jz4780_rng, REG_RNG_DATA);
+ jz4780_rng_writel(jz4780_rng, 0, REG_RNG_CTRL);
+
+ return 4;
+}
+
+static int jz4780_rng_probe(struct platform_device *pdev)
+{
+ struct jz4780_rng *jz4780_rng;
+ struct resource *res;
+
+ jz4780_rng = devm_kzalloc(&pdev->dev, sizeof(*jz4780_rng), GFP_KERNEL);
+ if (!jz4780_rng)
+ return -ENOMEM;
+
+ jz4780_rng->dev = &pdev->dev;
+ jz4780_rng->rng.name = "jz4780";
+ jz4780_rng->rng.read = jz4780_rng_read;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ jz4780_rng->mem = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(jz4780_rng->mem))
+ return PTR_ERR(jz4780_rng->mem);
+
+ return devm_hwrng_register(&pdev->dev, &jz4780_rng->rng);
+}
+
+static const struct of_device_id jz4780_rng_dt_match[] = {
+ { .compatible = "ingenic,jz4780-rng", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, jz4780_rng_dt_match);
+
+static struct platform_driver jz4780_rng_driver = {
+ .driver = {
+ .name = "jz4780-rng",
+ .of_match_table = jz4780_rng_dt_match,
+ },
+ .probe = jz4780_rng_probe,
+};
+module_platform_driver(jz4780_rng_driver);
+
+MODULE_DESCRIPTION("Ingenic JZ4780 H/W Random Number Generator driver");
+MODULE_AUTHOR("PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>");
+MODULE_LICENSE("GPL");
--
2.5.0
^ permalink raw reply related
* [PATCH v2 4/4] hw_random: jz4780-rng: Enable hardware RNG in CI20 defconfig
From: PrasannaKumar Muralidharan @ 2016-08-27 18:14 UTC (permalink / raw)
To: mpm-VDJrAJ4Gl5ZBDgjK7y7TUQ,
herbert-lOAM2aK0SrRLBo1qDEOMRrpzq4S04n8Q,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
ralf-6z/3iImG2C8G8FEW9MqTrA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
harvey.hunt-1AXoQHu6uovQT0dZR+AlfA, prarit-H+wXaHxf7aLQT0dZR+AlfA,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w,
joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA,
narmstrong-rdvid1DuHRBWk0Htik3J/w,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linux-crypto-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA
Cc: PrasannaKumar Muralidharan
In-Reply-To: <1472321697-3094-1-git-send-email-prasannatsmkumar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
This patch enables the usage of RNG in MIPS Creator CI20 default config.
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/mips/configs/ci20_defconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index bf164fe..51a47a4 100644
--- a/arch/mips/configs/ci20_defconfig
+++ b/arch/mips/configs/ci20_defconfig
@@ -88,7 +88,9 @@ CONFIG_SERIAL_8250_NR_UARTS=5
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
CONFIG_SERIAL_8250_INGENIC=y
CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_HW_RANDOM_JZ4780=y
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_GPIO_SYSFS=y
--
2.5.0
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^ permalink raw reply related
* [PATCH v2 1/4] hw_random: jz4780-rng: Add devicetree bindings for RNG in JZ4780 SoC
From: PrasannaKumar Muralidharan @ 2016-08-27 18:14 UTC (permalink / raw)
To: mpm-VDJrAJ4Gl5ZBDgjK7y7TUQ,
herbert-lOAM2aK0SrRLBo1qDEOMRrpzq4S04n8Q,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
ralf-6z/3iImG2C8G8FEW9MqTrA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
harvey.hunt-1AXoQHu6uovQT0dZR+AlfA, prarit-H+wXaHxf7aLQT0dZR+AlfA,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w,
joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA,
narmstrong-rdvid1DuHRBWk0Htik3J/w,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linux-crypto-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA
Cc: PrasannaKumar Muralidharan
In-Reply-To: <1472321697-3094-1-git-send-email-prasannatsmkumar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Add devicetree bindings for hardware random number generator present in
Ingenic JZ4780 SoC.
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/rng/ingenic,jz4780-rng.txt | 12 ++++++++++++
1 file changed, 12 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rng/ingenic,jz4780-rng.txt
diff --git a/Documentation/devicetree/bindings/rng/ingenic,jz4780-rng.txt b/Documentation/devicetree/bindings/rng/ingenic,jz4780-rng.txt
new file mode 100644
index 0000000..03abf56
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/ingenic,jz4780-rng.txt
@@ -0,0 +1,12 @@
+Ingenic jz4780 RNG driver
+
+Required properties:
+- compatible : Should be "ingenic,jz4780-rng"
+- reg : Specifies base physical address and size of the registers.
+
+Example:
+
+rng: rng@100000D8 {
+ compatible = "ingenic,jz4780-rng";
+ reg = <0x100000D8 0x8>;
+};
--
2.5.0
--
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^ permalink raw reply related
* [PATCH v2 0/4] hw_random: Add driver for Ingenic JZ4780 SoC RNG
From: PrasannaKumar Muralidharan @ 2016-08-27 18:14 UTC (permalink / raw)
To: mpm-VDJrAJ4Gl5ZBDgjK7y7TUQ,
herbert-lOAM2aK0SrRLBo1qDEOMRrpzq4S04n8Q,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
ralf-6z/3iImG2C8G8FEW9MqTrA,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
harvey.hunt-1AXoQHu6uovQT0dZR+AlfA, prarit-H+wXaHxf7aLQT0dZR+AlfA,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w,
joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA,
narmstrong-rdvid1DuHRBWk0Htik3J/w,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linux-crypto-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA
This is the v2 patch series that adds support for random number generator
present in Ingenic JZ4780 SoC.
Patch 1: Add device tree bindings for RNG in JZ4780 SoC.
Patch 2: Add Ingenic JZ4780 hardware RNG driver.
Patch 3: Add RNG to jz4780.dtsi.
Patch 4: Enable RNG in ci20_defconfig
PrasannaKumar Muralidharan (4):
hw_random: jz4780-rng: Add devicetree bindings for RNG in JZ4780 SoC
hw_random: jz4780-rng: Add Ingenic JZ4780 hardware RNG driver
hw_random: jz4780-rng: Add RNG node to jz4780.dtsi
hw_random: jz4780-rng: Enable hardware RNG in CI20 defconfig
Documentation/devicetree/bindings/rng/ingenic,jz4780-rng.txt | 12 +
MAINTAINERS | 5
arch/mips/boot/dts/ingenic/jz4780.dtsi | 7
arch/mips/configs/ci20_defconfig | 4
drivers/char/hw_random/Kconfig | 14 +
drivers/char/hw_random/Makefile | 1
drivers/char/hw_random/jz4780-rng.c | 102 +++++++++++
7 files changed, 143 insertions(+), 2 deletions(-)
--
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^ permalink raw reply
* Re: [PATCH v3 6/8] hwrng: amd: Replace global variable with private struct
From: Jason Cooper @ 2016-08-27 15:36 UTC (permalink / raw)
To: LABBE Corentin; +Cc: mpm, herbert, linux-crypto, linux-kernel
In-Reply-To: <20160827144331.GK10637@io.lakedaemon.net>
On Sat, Aug 27, 2016 at 02:43:31PM +0000, Jason Cooper wrote:
> Hi Corentin,
>
> On Fri, Aug 26, 2016 at 01:11:34PM +0200, LABBE Corentin wrote:
> > Instead of having two global variable, it's better to use a
> > private struct. This will permit to remove amd_pdev variable
> >
> > Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
> > ---
> > drivers/char/hw_random/amd-rng.c | 57 ++++++++++++++++++++++++++--------------
> > 1 file changed, 38 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c
> > index 383e197..4ef94e9 100644
> > --- a/drivers/char/hw_random/amd-rng.c
> > +++ b/drivers/char/hw_random/amd-rng.c
> > @@ -47,15 +47,18 @@ static const struct pci_device_id pci_tbl[] = {
> > };
> > MODULE_DEVICE_TABLE(pci, pci_tbl);
> >
> > -static struct pci_dev *amd_pdev;
> > +struct amd768_priv {
> > + struct pci_dev *pcidev;
> > + u32 pmbase;
> > +};
> >
> > static int amd_rng_data_present(struct hwrng *rng, int wait)
> > {
> > - u32 pmbase = (u32)rng->priv;
> > + struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
>
> Please remove unnecessary casts...
Hmm, I was assuming that, like other places in the tree, that priv was
declared void*. However, it's unsigned long in hw_random.h.
And, it looks like all users cast it. Either to a struct, or to a void
__iomem *.
So ignore what I said in my previous email. You can add my reviewed-by
without change.
It does look like /priv/ s/unsigned long/void */ would be a great
cleanup.
thx,
Jason.
^ permalink raw reply
* Re: [PATCH v3 0/8] hwrng: amd: rework of the amd hwrng driver
From: Jason Cooper @ 2016-08-27 14:49 UTC (permalink / raw)
To: LABBE Corentin; +Cc: mpm, herbert, linux-crypto, linux-kernel
In-Reply-To: <1472209896-17197-1-git-send-email-clabbe.montjoie@gmail.com>
Hi Corentin,
On Fri, Aug 26, 2016 at 01:11:28PM +0200, LABBE Corentin wrote:
> Changes since v2:
> - split the latest patch in 4
> Changes since v1:
> - Keep the hwrng name as "amd"
>
> LABBE Corentin (8):
> hwrng: amd: Fix style problem with blank line
> hwrng: amd: use the BIT macro
> hwrng: amd: Be consitent with the driver name
> hwrng: amd: Remove asm/io.h
> hwrng: amd: release_region must be called after hwrng_unregister
> hwrng: amd: Replace global variable with private struct
> hwrng: amd: Access hardware via ioread32/iowrite32
> hwrng: amd: Convert to new hwrng read() API
>
> drivers/char/hw_random/amd-rng.c | 150 +++++++++++++++++++++++++--------------
> 1 file changed, 96 insertions(+), 54 deletions(-)
Once you've fixed up the casting in #6, you can add my
Reviewed-by: Jason Cooper <jason@lakedaemon.net>
to the series.
thx,
Jason.
^ permalink raw reply
* Re: [PATCH v3 6/8] hwrng: amd: Replace global variable with private struct
From: Jason Cooper @ 2016-08-27 14:43 UTC (permalink / raw)
To: LABBE Corentin; +Cc: mpm, herbert, linux-crypto, linux-kernel
In-Reply-To: <1472209896-17197-7-git-send-email-clabbe.montjoie@gmail.com>
Hi Corentin,
On Fri, Aug 26, 2016 at 01:11:34PM +0200, LABBE Corentin wrote:
> Instead of having two global variable, it's better to use a
> private struct. This will permit to remove amd_pdev variable
>
> Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
> ---
> drivers/char/hw_random/amd-rng.c | 57 ++++++++++++++++++++++++++--------------
> 1 file changed, 38 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/char/hw_random/amd-rng.c b/drivers/char/hw_random/amd-rng.c
> index 383e197..4ef94e9 100644
> --- a/drivers/char/hw_random/amd-rng.c
> +++ b/drivers/char/hw_random/amd-rng.c
> @@ -47,15 +47,18 @@ static const struct pci_device_id pci_tbl[] = {
> };
> MODULE_DEVICE_TABLE(pci, pci_tbl);
>
> -static struct pci_dev *amd_pdev;
> +struct amd768_priv {
> + struct pci_dev *pcidev;
> + u32 pmbase;
> +};
>
> static int amd_rng_data_present(struct hwrng *rng, int wait)
> {
> - u32 pmbase = (u32)rng->priv;
> + struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
Please remove unnecessary casts...
> int data, i;
>
> for (i = 0; i < 20; i++) {
> - data = !!(inl(pmbase + 0xF4) & 1);
> + data = !!(inl(priv->pmbase + 0xF4) & 1);
> if (data || !wait)
> break;
> udelay(10);
> @@ -65,35 +68,37 @@ static int amd_rng_data_present(struct hwrng *rng, int wait)
>
> static int amd_rng_data_read(struct hwrng *rng, u32 *data)
> {
> - u32 pmbase = (u32)rng->priv;
> + struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
here,
>
> - *data = inl(pmbase + 0xF0);
> + *data = inl(priv->pmbase + 0xF0);
>
> return 4;
> }
>
> static int amd_rng_init(struct hwrng *rng)
> {
> + struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
here,
> u8 rnen;
>
> - pci_read_config_byte(amd_pdev, 0x40, &rnen);
> + pci_read_config_byte(priv->pcidev, 0x40, &rnen);
> rnen |= BIT(7); /* RNG on */
> - pci_write_config_byte(amd_pdev, 0x40, rnen);
> + pci_write_config_byte(priv->pcidev, 0x40, rnen);
>
> - pci_read_config_byte(amd_pdev, 0x41, &rnen);
> + pci_read_config_byte(priv->pcidev, 0x41, &rnen);
> rnen |= BIT(7); /* PMIO enable */
> - pci_write_config_byte(amd_pdev, 0x41, rnen);
> + pci_write_config_byte(priv->pcidev, 0x41, rnen);
>
> return 0;
> }
>
> static void amd_rng_cleanup(struct hwrng *rng)
> {
> + struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
here,
> u8 rnen;
>
> - pci_read_config_byte(amd_pdev, 0x40, &rnen);
> + pci_read_config_byte(priv->pcidev, 0x40, &rnen);
> rnen &= ~BIT(7); /* RNG off */
> - pci_write_config_byte(amd_pdev, 0x40, rnen);
> + pci_write_config_byte(priv->pcidev, 0x40, rnen);
> }
>
> static struct hwrng amd_rng = {
> @@ -110,6 +115,7 @@ static int __init mod_init(void)
> struct pci_dev *pdev = NULL;
> const struct pci_device_id *ent;
> u32 pmbase;
> + struct amd768_priv *priv;
>
> for_each_pci_dev(pdev) {
> ent = pci_match_id(pci_tbl, pdev);
> @@ -117,24 +123,30 @@ static int __init mod_init(void)
> goto found;
> }
> /* Device not found. */
> - goto out;
> + return -ENODEV;
>
> found:
> err = pci_read_config_dword(pdev, 0x58, &pmbase);
> if (err)
> - goto out;
> - err = -EIO;
> + return err;
> +
> pmbase &= 0x0000FF00;
> if (pmbase == 0)
> - goto out;
> + return -EIO;
> +
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> if (!request_region(pmbase + 0xF0, 8, DRV_NAME)) {
> dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
> pmbase + 0xF0);
> err = -EBUSY;
> goto out;
> }
> - amd_rng.priv = (unsigned long)pmbase;
> - amd_pdev = pdev;
> + amd_rng.priv = (unsigned long)priv;
here,
> + priv->pmbase = pmbase;
> + priv->pcidev = pdev;
>
> pr_info(DRV_NAME " detected\n");
> err = hwrng_register(&amd_rng);
> @@ -143,17 +155,24 @@ found:
> release_region(pmbase + 0xF0, 8);
> goto out;
> }
> + return 0;
> +
> out:
> + kfree(priv);
> return err;
> }
>
> static void __exit mod_exit(void)
> {
> - u32 pmbase = (unsigned long)amd_rng.priv;
> + struct amd768_priv *priv;
> +
> + priv = (struct amd768_priv *)amd_rng.priv;
and here.
thx,
Jason.
>
> hwrng_unregister(&amd_rng);
>
> - release_region(pmbase + 0xF0, 8);
> + release_region(priv->pmbase + 0xF0, 8);
> +
> + kfree(priv);
> }
>
> module_init(mod_init);
> --
> 2.7.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-crypto" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: Git bisected regression for ipsec/aead
From: Sowmini Varadhan @ 2016-08-27 10:13 UTC (permalink / raw)
To: Herbert Xu; +Cc: linux-crypto, joshua.a.hay, steffen.klassert
In-Reply-To: <20160825084951.GA11496@gondor.apana.org.au>
On (08/25/16 16:49), Herbert Xu wrote:
>
> On Fri, Aug 19, 2016 at 03:21:24PM -0400, Sowmini Varadhan wrote:
> > 7271b33cb87e80f3a416fb031ad3ca87f0bea80a is the first bad commit
> This bisection doesn't make much sense as this patch just causes
> cryptd to be used a little more more frequently. But it does
> point the finger at cryptd.
On additional testing, I think this might be related to some
subtle race/timing issue so that git-bisect may not necessarily
be able to pin-point the correct bad-commit: if I add a few
printks in other parts of the IPsec stack (and change the timing),
the problem does not reproduce. Let me try to collect more data
on this.
Meanwhile, if you can see some bug in the commit above, then
it probably makes sense to fix it upstream anyway.
--Sowmini
^ permalink raw reply
* caam - IV source for IPsec decryption
From: Horia Ioan Geanta Neag @ 2016-08-25 16:12 UTC (permalink / raw)
To: Herbert Xu; +Cc: linux-crypto@vger.kernel.org
Herbert,
Commits
7021b2e1cddd "esp4: Switch to new AEAD interface"
000ae7b2690e "esp6: Switch to new AEAD interface"
removed the following:
/* Get ivec. This can be wrong, check against another impls. */
iv = esph->enc_data;
from IPsec decryption - esp{4,6}_input(),
so the IV in req->iv received by the implementer is no longer valid.
Thus, the load of IV in caam driver - caamalg.c, init_authenc_job():
if (ivsize && (is_rfc3686 || !(alg->caam.geniv && encrypt)))
append_load_as_imm(desc, req->iv, ivsize,
LDST_CLASS_1_CCB |
LDST_SRCDST_BYTE_CONTEXT |
(ivoffset << LDST_OFFSET_SHIFT));
is not suited for case mentioned above.
Instead, the IV should be read from the req->src scatterlist
(which consists of assoc data, iv, ciphertext).
Please let me know if this is accurate, so I could prepare a fix.
Thanks,
Horia
^ permalink raw reply
* [PATCH] hw_random: Remove check for max less than 4 bytes
From: PrasannaKumar Muralidharan @ 2016-08-26 18:32 UTC (permalink / raw)
To: mpm, herbert, linux-crypto, linux-kernel; +Cc: PrasannaKumar Muralidharan
HW RNG core never asks for data less than 4 bytes. The check whether max
is less than 4 bytes is unnecessary. Remove the check.
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
drivers/char/hw_random/meson-rng.c | 3 ---
drivers/char/hw_random/st-rng.c | 3 ---
2 files changed, 6 deletions(-)
diff --git a/drivers/char/hw_random/meson-rng.c b/drivers/char/hw_random/meson-rng.c
index 0cfd81b..58bef39 100644
--- a/drivers/char/hw_random/meson-rng.c
+++ b/drivers/char/hw_random/meson-rng.c
@@ -76,9 +76,6 @@ static int meson_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
struct meson_rng_data *data =
container_of(rng, struct meson_rng_data, rng);
- if (max < sizeof(u32))
- return 0;
-
*(u32 *)buf = readl_relaxed(data->base + RNG_DATA);
return sizeof(u32);
diff --git a/drivers/char/hw_random/st-rng.c b/drivers/char/hw_random/st-rng.c
index 1d35363..7e8aa6b 100644
--- a/drivers/char/hw_random/st-rng.c
+++ b/drivers/char/hw_random/st-rng.c
@@ -54,9 +54,6 @@ static int st_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
u32 status;
int i;
- if (max < sizeof(u16))
- return -EINVAL;
-
/* Wait until FIFO is full - max 4uS*/
for (i = 0; i < ST_RNG_FILL_FIFO_TIMEOUT; i++) {
status = readl_relaxed(ddata->base + ST_RNG_STATUS_REG);
--
2.5.0
^ permalink raw reply related
* [PATCH v2] crypto: caam - fix IV loading for authenc (giv)decryption
From: Horia Geantă @ 2016-08-26 15:17 UTC (permalink / raw)
To: Herbert Xu; +Cc: linux-crypto, David S. Miller
For algorithms that implement IV generators before the crypto ops,
the IV needed for decryption is initially located in req->src
scatterlist, not in req->iv.
Avoid copying the IV into req->iv by modifying the (givdecrypt)
descriptors to load it directly from req->src.
aead_givdecrypt() is no longer needed and goes away.
Cc: <stable@vger.kernel.org> # 4.3+
Fixes: 479bcc7c5b9e ("crypto: caam - Convert authenc to new AEAD interface")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
drivers/crypto/caam/caamalg.c | 77 +++++++++++++++++++++----------------------
1 file changed, 37 insertions(+), 40 deletions(-)
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 6dc597126b79..775b8b524913 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -556,7 +556,10 @@ skip_enc:
/* Read and write assoclen bytes */
append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+ if (alg->caam.geniv)
+ append_math_add_imm_u32(desc, VARSEQOUTLEN, REG3, IMM, ivsize);
+ else
+ append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
/* Skip assoc data */
append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
@@ -565,6 +568,14 @@ skip_enc:
append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
KEY_VLF);
+ if (alg->caam.geniv) {
+ append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
+ LDST_SRCDST_BYTE_CONTEXT |
+ (ctx1_iv_off << LDST_OFFSET_SHIFT));
+ append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO |
+ (ctx1_iv_off << MOVE_OFFSET_SHIFT) | ivsize);
+ }
+
/* Load Counter into CONTEXT1 reg */
if (is_rfc3686)
append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM |
@@ -2150,7 +2161,7 @@ static void init_authenc_job(struct aead_request *req,
init_aead_job(req, edesc, all_contig, encrypt);
- if (ivsize && (is_rfc3686 || !(alg->caam.geniv && encrypt)))
+ if (ivsize && !alg->caam.geniv)
append_load_as_imm(desc, req->iv, ivsize,
LDST_CLASS_1_CCB |
LDST_SRCDST_BYTE_CONTEXT |
@@ -2537,20 +2548,6 @@ static int aead_decrypt(struct aead_request *req)
return ret;
}
-static int aead_givdecrypt(struct aead_request *req)
-{
- struct crypto_aead *aead = crypto_aead_reqtfm(req);
- unsigned int ivsize = crypto_aead_ivsize(aead);
-
- if (req->cryptlen < ivsize)
- return -EINVAL;
-
- req->cryptlen -= ivsize;
- req->assoclen += ivsize;
-
- return aead_decrypt(req);
-}
-
/*
* allocate and map the ablkcipher extended descriptor for ablkcipher
*/
@@ -3210,7 +3207,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
},
@@ -3256,7 +3253,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
},
@@ -3302,7 +3299,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
},
@@ -3348,7 +3345,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
},
@@ -3394,7 +3391,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA384_DIGEST_SIZE,
},
@@ -3440,7 +3437,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA512_DIGEST_SIZE,
},
@@ -3486,7 +3483,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
},
@@ -3534,7 +3531,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
},
@@ -3582,7 +3579,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
},
@@ -3630,7 +3627,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
},
@@ -3678,7 +3675,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA384_DIGEST_SIZE,
},
@@ -3726,7 +3723,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA512_DIGEST_SIZE,
},
@@ -3772,7 +3769,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
},
@@ -3818,7 +3815,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
},
@@ -3864,7 +3861,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
},
@@ -3910,7 +3907,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
},
@@ -3956,7 +3953,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA384_DIGEST_SIZE,
},
@@ -4002,7 +3999,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA512_DIGEST_SIZE,
},
@@ -4051,7 +4048,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
},
@@ -4102,7 +4099,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
},
@@ -4153,7 +4150,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
},
@@ -4204,7 +4201,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
},
@@ -4255,7 +4252,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = SHA384_DIGEST_SIZE,
},
@@ -4306,7 +4303,7 @@ static struct caam_aead_alg driver_aeads[] = {
.setkey = aead_setkey,
.setauthsize = aead_setauthsize,
.encrypt = aead_encrypt,
- .decrypt = aead_givdecrypt,
+ .decrypt = aead_decrypt,
.ivsize = CTR_RFC3686_IV_SIZE,
.maxauthsize = SHA512_DIGEST_SIZE,
},
--
2.4.4
^ permalink raw reply related
* crypto: xor - Fix warning when XOR_SELECT_TEMPLATE is unset
From: Herbert Xu @ 2016-08-26 15:19 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Martin Schwidefsky, linux-next, linux-kernel,
Linux Crypto Mailing List
In-Reply-To: <20160825211411.08858397@canb.auug.org.au>
On Thu, Aug 25, 2016 at 09:14:11PM +1000, Stephen Rothwell wrote:
>
> That looks fine to me. An alternative might be to have:
>
> #ifndef XOR_SELECT_TEMPLATE
> #define XOR_SELECT_TEMPLATE(x) (x)
> #endif
>
> near the top of the file. That gets the #ifdef out of the code flow
> and serves as some hint that such a thing can be defined by arch header
> files.
Good idea. Thanks Stephen.
---8<---
This patch fixes an unused label warning triggered when the macro
XOR_SELECT_TEMPLATE is not set.
Fixes: 39457acda913 ("crypto: xor - skip speed test if the xor...")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Suggested-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
diff --git a/crypto/xor.c b/crypto/xor.c
index b8975d9..263af9f 100644
--- a/crypto/xor.c
+++ b/crypto/xor.c
@@ -24,6 +24,10 @@
#include <linux/preempt.h>
#include <asm/xor.h>
+#ifndef XOR_SELECT_TEMPLATE
+#define XOR_SELECT_TEMPLATE(x) (x)
+#endif
+
/* The xor routines to use. */
static struct xor_block_template *active_template;
@@ -109,17 +113,14 @@ calibrate_xor_blocks(void)
void *b1, *b2;
struct xor_block_template *f, *fastest;
- fastest = NULL;
+ fastest = XOR_SELECT_TEMPLATE(NULL);
-#ifdef XOR_SELECT_TEMPLATE
- fastest = XOR_SELECT_TEMPLATE(fastest);
if (fastest) {
printk(KERN_INFO "xor: automatically using best "
"checksumming function %-10s\n",
fastest->name);
goto out;
}
-#endif
/*
* Note: Since the memory is not actually used for _anything_ but to
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply related
* Re: [PATCH -next v2] chcr: Fix non static symbol warning
From: Herbert Xu @ 2016-08-26 14:42 UTC (permalink / raw)
To: Wei Yongjun
Cc: David S. Miller, Hariprasad Shenai, Atul Gupta, Wei Yongjun,
linux-crypto, netdev
In-Reply-To: <1472221268-25123-1-git-send-email-weiyj.lk@gmail.com>
On Fri, Aug 26, 2016 at 02:21:08PM +0000, Wei Yongjun wrote:
> From: Wei Yongjun <weiyongjun1@huawei.com>
>
> Fixes the following sparse warning:
>
> drivers/crypto/chelsio/chcr_algo.c:593:5: warning:
> symbol 'cxgb4_is_crypto_q_full' was not declared. Should it be static?
>
> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH] crypto: caam - fix IV loading for authenc (giv)decryption
From: Herbert Xu @ 2016-08-26 14:39 UTC (permalink / raw)
To: Horia Geantă; +Cc: linux-crypto, David S. Miller
In-Reply-To: <1472220822-18888-1-git-send-email-horia.geanta@nxp.com>
On Fri, Aug 26, 2016 at 05:13:42PM +0300, Horia Geantă wrote:
>
> In terms of optimizations, would it be safe to assume all "geniv" authenc
> algorithms - {echainiv, seqiv}(authenc) - get assoc,iv,ciphertext in
> req->src for decryption?
Yes. They all get the raw IPsec packet, apart from the ESN munging.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* [PATCH -next v2] chcr: Fix non static symbol warning
From: Wei Yongjun @ 2016-08-26 14:21 UTC (permalink / raw)
To: Herbert Xu, David S. Miller, Hariprasad Shenai, Atul Gupta
Cc: Wei Yongjun, linux-crypto, netdev
In-Reply-To: <1471882278-25777-1-git-send-email-weiyj.lk@gmail.com>
From: Wei Yongjun <weiyongjun1@huawei.com>
Fixes the following sparse warning:
drivers/crypto/chelsio/chcr_algo.c:593:5: warning:
symbol 'cxgb4_is_crypto_q_full' was not declared. Should it be static?
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
v1 -> v2: cc netdev maillist
---
drivers/crypto/chelsio/chcr_algo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c
index ad8e353..e4ddb92 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -590,7 +590,7 @@ badkey_err:
return -EINVAL;
}
-int cxgb4_is_crypto_q_full(struct net_device *dev, unsigned int idx)
+static int cxgb4_is_crypto_q_full(struct net_device *dev, unsigned int idx)
{
int ret = 0;
struct sge_ofld_txq *q;
^ permalink raw reply related
* [PATCH] crypto: caam - fix IV loading for authenc (giv)decryption
From: Horia Geantă @ 2016-08-26 14:13 UTC (permalink / raw)
To: Herbert Xu; +Cc: linux-crypto, David S. Miller
For algorithms that implement IV generators before the crypto ops,
the IV needed for decryption is initially located in req->src
scatterlist, not in req->iv.
aead_givdecrypt() is updated to put the IV in place.
Cc: <stable@vger.kernel.org> # 4.3+
Fixes: 479bcc7c5b9e ("crypto: caam - Convert authenc to new AEAD interface")
Suggested-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
Herbert, as you suggested, aead_givdecrypt() is now setting the IV.
In terms of optimizations, would it be safe to assume all "geniv" authenc
algorithms - {echainiv, seqiv}(authenc) - get assoc,iv,ciphertext in
req->src for decryption?
The idea would be to avoid copying IV into req->iv and instruct
the crypto engine to access it directly from req->src scatterlist.
drivers/crypto/caam/caamalg.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 6dc597126b79..78be2bea1273 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -2545,6 +2545,7 @@ static int aead_givdecrypt(struct aead_request *req)
if (req->cryptlen < ivsize)
return -EINVAL;
+ scatterwalk_map_and_copy(req->iv, req->src, req->assoclen, ivsize, 0);
req->cryptlen -= ivsize;
req->assoclen += ivsize;
--
2.4.4
^ permalink raw reply related
* Re: [PATCH v2 5/5] hwrng: amd: Rework of the amd768-hwrng driver
From: Jason Cooper @ 2016-08-26 13:29 UTC (permalink / raw)
To: LABBE Corentin; +Cc: mpm, herbert, linux-crypto, linux-kernel
In-Reply-To: <20160826083802.GA32290@Red>
Hi Corentin,
On Fri, Aug 26, 2016 at 10:38:02AM +0200, LABBE Corentin wrote:
> On Thu, Aug 25, 2016 at 02:56:38PM +0000, Jason Cooper wrote:
> > On Thu, Aug 25, 2016 at 02:16:35PM +0200, LABBE Corentin wrote:
> > > This patch convert the hwrng interface used by amd768-rng to its new API
> > > by replacing data_read()/data_present() by read().
> > >
> > > Furthermore, Instead of having two global variable, it's better to use a
> > > private struct. This will permit to remove amd_pdev variable.
> > >
> > > Finally, Instead of accessing hw directly via pmbase, it's better to
> > > access after ioport_map() via ioread32/iowrite32.
> >
> > I was going to recommend a better $subject line, but now I see why it's
> > vague. :( I would recommend breaking this patch up into three:
> >
> > hwrng: amd - Access hardware via ioread32/iowrite32
> > hwrng: amd - Replace global variable with private struct
> > hwrng: amd - Convert to new hwrng read() API
> >
>
> That was my first idea, but believed that it wasnt worth it.
When working with crypto/rng code, I'm a firm believer in moving
cautiously and deliberately. :-)
> Anyway I will do it.
Thanks!
thx,
Jason.
^ permalink raw reply
* Re: caam - IV source for IPsec decryption
From: Herbert Xu @ 2016-08-26 11:39 UTC (permalink / raw)
To: Horia Ioan Geanta Neag; +Cc: linux-crypto@vger.kernel.org
In-Reply-To: <DB4PR04MB0847411DA278511045969E6998ED0@DB4PR04MB0847.eurprd04.prod.outlook.com>
On Thu, Aug 25, 2016 at 04:12:35PM +0000, Horia Ioan Geanta Neag wrote:
> Herbert,
>
> Commits
> 7021b2e1cddd "esp4: Switch to new AEAD interface"
> 000ae7b2690e "esp6: Switch to new AEAD interface"
> removed the following:
> /* Get ivec. This can be wrong, check against another impls. */
> iv = esph->enc_data;
> from IPsec decryption - esp{4,6}_input(),
> so the IV in req->iv received by the implementer is no longer valid.
>
> Thus, the load of IV in caam driver - caamalg.c, init_authenc_job():
> if (ivsize && (is_rfc3686 || !(alg->caam.geniv && encrypt)))
> append_load_as_imm(desc, req->iv, ivsize,
> LDST_CLASS_1_CCB |
> LDST_SRCDST_BYTE_CONTEXT |
> (ivoffset << LDST_OFFSET_SHIFT));
> is not suited for case mentioned above.
>
> Instead, the IV should be read from the req->src scatterlist
> (which consists of assoc data, iv, ciphertext).
> Please let me know if this is accurate, so I could prepare a fix.
For authenc req->iv will be set by echainiv. But yes I seem to
have screwed this up for the echainiv ones in caam. You need to
change aead_givdecrypt to set req->iv.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* caam - IV source for IPsec decryption
From: Horia Ioan Geanta Neag @ 2016-08-26 7:40 UTC (permalink / raw)
To: Herbert Xu; +Cc: linux-crypto@vger.kernel.org
Herbert,
Commits
7021b2e1cddd "esp4: Switch to new AEAD interface"
000ae7b2690e "esp6: Switch to new AEAD interface"
removed the following:
/* Get ivec. This can be wrong, check against another impls. */
iv = esph->enc_data;
from IPsec decryption - esp{4,6}_input(),
so the IV in req->iv received by the implementer is no longer valid.
Thus, the load of IV in caam driver - caamalg.c, init_authenc_job():
if (ivsize && (is_rfc3686 || !(alg->caam.geniv && encrypt)))
append_load_as_imm(desc, req->iv, ivsize,
LDST_CLASS_1_CCB |
LDST_SRCDST_BYTE_CONTEXT |
(ivoffset << LDST_OFFSET_SHIFT));
is not suited for case mentioned above.
Instead, the IV should be read from the req->src scatterlist
(which consists of assoc data, iv, ciphertext).
Please let me know if this is accurate, so I could prepare a fix.
Thanks,
Horia
^ permalink raw reply
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