* [PATCH] crypto: mediatek: don't return garbage err on successful return
From: Colin King @ 2017-01-03 13:21 UTC (permalink / raw)
To: Herbert Xu, David S . Miller, Matthias Brugger, Ryder Lee,
linux-crypto-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA
From: Colin Ian King <colin.king-Z7WLFzj8eWMS+FvcfC7Uqw@public.gmane.org>
In the case where keylen <= bs mtk_sha_setkey returns an uninitialized
return value in err. Fix this by returning 0 instead of err.
Issue detected by static analysis with cppcheck.
Signed-off-by: Colin Ian King <colin.king-Z7WLFzj8eWMS+FvcfC7Uqw@public.gmane.org>
---
drivers/crypto/mediatek/mtk-sha.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/mediatek/mtk-sha.c b/drivers/crypto/mediatek/mtk-sha.c
index 8951363..8e1b440 100644
--- a/drivers/crypto/mediatek/mtk-sha.c
+++ b/drivers/crypto/mediatek/mtk-sha.c
@@ -878,7 +878,7 @@ static int mtk_sha_setkey(struct crypto_ahash *tfm,
bctx->opad[i] ^= 0x5c;
}
- return err;
+ return 0;
}
static int mtk_sha_export(struct ahash_request *req, void *out)
--
2.10.2
^ permalink raw reply related
* Re: [RFC PATCH v2] crypto: Add IV generation algorithms
From: Gilad Ben-Yossef @ 2017-01-03 14:23 UTC (permalink / raw)
To: Binoy Jayan
Cc: Oded, Ofir, Herbert Xu, David S. Miller, linux-crypto, Mark Brown,
Arnd Bergmann, linux-kernel, Alasdair Kergon, Mike Snitzer,
dm-devel, Shaohua Li, linux-raid, Rajendra, gilad.benyossef
In-Reply-To: <1481618949-20086-2-git-send-email-binoy.jayan@linaro.org>
Hi Binoy,
On Tue, Dec 13, 2016 at 02:19:09PM +0530, Binoy Jayan wrote:
> Currently, the iv generation algorithms are implemented in dm-crypt.c.
> The goal is to move these algorithms from the dm layer to the kernel
> crypto layer by implementing them as template ciphers so they can be
> implemented in hardware for performance. As part of this patchset, the
> iv-generation code is moved from the dm layer to the crypto layer and
> adapt the dm-layer to send a whole 'bio' (as defined in the block layer)
> at a time. Each bio contains the in memory representation of physically
> contiguous disk blocks. The dm layer sets up a chained scatterlist of
> these blocks split into physically contiguous segments in memory so that
> DMA can be performed. The iv generation algorithms implemented in geniv.c
> include plain, plain64, essiv, benbi, null, lmk and tcw.
>
Good idea. I wanted to test the patch but alas it does not apply cleanly.
You seem to have a blank line at the end of files and other small
transgressions that makes checkpatch grumpy.
<snip>
Also...
>
> Not-signed-off-by: Binoy Jayan <binoy.jayan@linaro.org>
What is Not-signed-off-by ? :-)
Thanks,
Gilad Ben-Yossef
^ permalink raw reply
* Re: Geode LX AES/RNG driver triggers warning
From: One Thousand Gnomes @ 2017-01-03 14:52 UTC (permalink / raw)
To: David Gstir
Cc: linux-geode, linux-crypto, linux-kernel, teheo, prasannatsmkumar,
Richard Weinberger
In-Reply-To: <A0185338-47A4-42BE-B2D4-F1EB082593E3@sigma-star.at>
On Sat, 31 Dec 2016 00:58:54 +0100
David Gstir <david@sigma-star.at> wrote:
> Hi!
>
> I recently tested kernel v4.9 on my AMD Geode platform and noticed that its AES hardware driver triggers this warning on initialization:
...
> I narrowed it down to commit 6e9b5e76882c ("hwrng: geode - Migrate to managed API") which seems to introduce this. It looks to me like some issue between devres, the Geode hwrng and AES drivers which both use the same PCI device.
It does
> I'm no expert here, but I curious if this will cause any issues when using the hardware crypto drivers and also what's the best way to get rid of this?
Probably to create an mfd device that turns the PCI device into two MFD
devices and bind AES and hwrng one to each MFD device. Take a look in
drivers/mfd. That would also fix the uglies in mod_init for the rng
driver.
Alan
^ permalink raw reply
* Re: [PATCH 0/6] crypto: ARM/arm64 - AES and ChaCha20 updates for v4.11
From: Ard Biesheuvel @ 2017-01-03 20:01 UTC (permalink / raw)
To: linux-crypto@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org, Herbert Xu, Ard Biesheuvel
In-Reply-To: <1483381268-12987-1-git-send-email-ard.biesheuvel@linaro.org>
On 2 January 2017 at 18:21, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> This series adds SIMD implementations for arm64 and ARM of ChaCha20 (*),
> and a port of the ARM bit-sliced AES algorithm to arm64, and
>
> Patch #1 is a prerequisite for the AES-XTS implementation in #6, which needs
> a secondary AES transform to generate the initial tweak.
>
Herbert,
I actually have a scalar AES implementation for arm64 which I could
use instead, making this patch unnecessary.
I could respin the entire series, or you could simply disregard #1 and
#6 for now, whichever you prefer.
Thanks,
Ard.
> Patch #2 optimizes the bit-sliced AES glue code for ARM to iterate over the
> input in the most efficient manner possible.
>
> Patch #3 adds a NEON implementation of ChaCha20 for ARM.
>
> Patch #4 adds a NEON implementation of ChaCha20 for arm64.
>
> Patch #5 modifies the existing NEON and ARMv8 Crypto Extensions implementations
> of AES-CTR to be available as a synchronous skcipher as well. This is intended
> for the mac80211 code, which uses synchronous encapsulations of ctr(aes)
> [ccm, gcm] in softirq context, which supports SIMD algorithms on arm64.
>
> Patch #6 adds a port of the ARM bit-sliced AES code to arm64, in ECB, CTR
> and XTS modes.
>
> Ard Biesheuvel (6):
> crypto: generic/aes - export encrypt and decrypt entry points
> crypto: arm/aes-neonbs - process 8 blocks in parallel if we can
> crypto: arm/chacha20 - implement NEON version based on SSE3 code
> crypto: arm64/chacha20 - implement NEON version based on SSE3 code
> crypto: arm64/aes-blk - expose AES-CTR as synchronous cipher as well
> crypto: arm64/aes - reimplement bit-sliced ARM/NEON implementation for
> arm64
>
> arch/arm/crypto/Kconfig | 6 +
> arch/arm/crypto/Makefile | 2 +
> arch/arm/crypto/aesbs-glue.c | 67 +-
> arch/arm/crypto/chacha20-neon-core.S | 524 ++++++++++++
> arch/arm/crypto/chacha20-neon-glue.c | 128 +++
> arch/arm64/crypto/Kconfig | 13 +
> arch/arm64/crypto/Makefile | 6 +
> arch/arm64/crypto/aes-glue.c | 25 +-
> arch/arm64/crypto/aes-neonbs-core.S | 879 ++++++++++++++++++++
> arch/arm64/crypto/aes-neonbs-glue.c | 344 ++++++++
> arch/arm64/crypto/chacha20-neon-core.S | 450 ++++++++++
> arch/arm64/crypto/chacha20-neon-glue.c | 127 +++
> crypto/aes_generic.c | 10 +-
> include/crypto/aes.h | 3 +
> 14 files changed, 2549 insertions(+), 35 deletions(-)
> create mode 100644 arch/arm/crypto/chacha20-neon-core.S
> create mode 100644 arch/arm/crypto/chacha20-neon-glue.c
> create mode 100644 arch/arm64/crypto/aes-neonbs-core.S
> create mode 100644 arch/arm64/crypto/aes-neonbs-glue.c
> create mode 100644 arch/arm64/crypto/chacha20-neon-core.S
> create mode 100644 arch/arm64/crypto/chacha20-neon-glue.c
>
> --
> 2.7.4
>
^ permalink raw reply
* Re: [RFC PATCH v2] crypto: Add IV generation algorithms
From: Binoy Jayan @ 2017-01-04 5:20 UTC (permalink / raw)
To: Gilad Ben-Yossef
Cc: Oded, Ofir, Herbert Xu, David S. Miller, linux-crypto, Mark Brown,
Arnd Bergmann, Linux kernel mailing list, Alasdair Kergon,
Mike Snitzer, dm-devel, Shaohua Li, linux-raid, Rajendra,
gilad.benyossef
In-Reply-To: <CAOtvUMc_X1DUuR8NTvOLjW7h-p=X14tFHFqe_dB8t08-nYBPcw@mail.gmail.com>
Hi Gilad,
On 3 January 2017 at 19:53, Gilad Ben-Yossef <gilad@benyossef.com> wrote:
> Good idea. I wanted to test the patch but alas it does not apply cleanly.
> You seem to have a blank line at the end of files and other small
> transgressions that makes checkpatch grumpy.
I think that is because there were some key structure changes in dm-crypt
after I sent out v2. I have resolved them while working on v3. Please wait for
the next version of the patchset. I'll send it probably by next week.
I wanted to incorporate a few changes suggested by Herbert before sending them.
> What is Not-signed-off-by ? :-)
It was just an RFC patch, not ready for merging.
Thanks,
Binoy
^ permalink raw reply
* Re: [PATCH] crypto: Replaced gcc specific attributes with macros from compiler.h
From: Gideon D'souza @ 2017-01-04 15:15 UTC (permalink / raw)
To: linux-kernel@vger.kernel.org, davem, nhorman, Joe Perches,
Andrew Morton, linux-crypto, Geert Uytterhoeven
Any update on this patch, should I base it on another tree, this was
based off of linus's tree right when he released 4.10-rc2
Should I send it close to the next merge window?
On Sat, Dec 31, 2016 at 9:26 PM, <gidisrael@gmail.com> wrote:
> From: Gideon Israel Dsouza <gidisrael@gmail.com>
>
> Continuing from this commit: 52f5684c8e1e
> ("kernel: use macros from compiler.h instead of __attribute__((...))")
>
> I submitted 4 total patches. They are part of task I've taken up to
> increase compiler portability in the kernel. I've cleaned up the
> subsystems under /kernel /mm /block and /security, this patch targets
> /crypto.
>
> There is <linux/compiler.h> which provides macros for various gcc specific
> constructs. Eg: __weak for __attribute__((weak)). I've cleaned all
> instances of gcc specific attributes with the right macros for the crypto
> subsystem.
>
> I had to make one additional change into compiler-gcc.h for the case when
> one wants to use this: __attribute__((aligned) and not specify an alignment
> factor. From the gcc docs, this will result in the largest alignment for
> that data type on the target machine so I've named the macro
> __aligned_largest. Please advise if another name is more appropriate.
>
> Signed-off-by: Gideon Israel Dsouza <gidisrael@gmail.com>
> ---
> crypto/ablkcipher.c | 5 +++--
> crypto/acompress.c | 3 ++-
> crypto/aead.c | 3 ++-
> crypto/ahash.c | 3 ++-
> crypto/akcipher.c | 3 ++-
> crypto/blkcipher.c | 7 ++++---
> crypto/cts.c | 5 +++--
> crypto/kpp.c | 3 ++-
> crypto/pcbc.c | 3 ++-
> crypto/rng.c | 3 ++-
> crypto/scompress.c | 3 ++-
> crypto/shash.c | 9 +++++----
> crypto/skcipher.c | 3 ++-
> include/linux/compiler-gcc.h | 1 +
> 14 files changed, 34 insertions(+), 20 deletions(-)
>
> diff --git a/crypto/ablkcipher.c b/crypto/ablkcipher.c
> index d676fc5..d880a48 100644
> --- a/crypto/ablkcipher.c
> +++ b/crypto/ablkcipher.c
> @@ -19,6 +19,7 @@
> #include <linux/slab.h>
> #include <linux/seq_file.h>
> #include <linux/cryptouser.h>
> +#include <linux/compiler.h>
> #include <net/netlink.h>
>
> #include <crypto/scatterwalk.h>
> @@ -394,7 +395,7 @@ static int crypto_ablkcipher_report(struct sk_buff *skb, struct crypto_alg *alg)
> #endif
>
> static void crypto_ablkcipher_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
> static void crypto_ablkcipher_show(struct seq_file *m, struct crypto_alg *alg)
> {
> struct ablkcipher_alg *ablkcipher = &alg->cra_ablkcipher;
> @@ -468,7 +469,7 @@ static int crypto_givcipher_report(struct sk_buff *skb, struct crypto_alg *alg)
> #endif
>
> static void crypto_givcipher_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
> static void crypto_givcipher_show(struct seq_file *m, struct crypto_alg *alg)
> {
> struct ablkcipher_alg *ablkcipher = &alg->cra_ablkcipher;
> diff --git a/crypto/acompress.c b/crypto/acompress.c
> index 887783d..47d1162 100644
> --- a/crypto/acompress.c
> +++ b/crypto/acompress.c
> @@ -20,6 +20,7 @@
> #include <linux/crypto.h>
> #include <crypto/algapi.h>
> #include <linux/cryptouser.h>
> +#include <linux/compiler.h>
> #include <net/netlink.h>
> #include <crypto/internal/acompress.h>
> #include <crypto/internal/scompress.h>
> @@ -50,7 +51,7 @@ static int crypto_acomp_report(struct sk_buff *skb, struct crypto_alg *alg)
> #endif
>
> static void crypto_acomp_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
>
> static void crypto_acomp_show(struct seq_file *m, struct crypto_alg *alg)
> {
> diff --git a/crypto/aead.c b/crypto/aead.c
> index 3f5c5ff..f794b30 100644
> --- a/crypto/aead.c
> +++ b/crypto/aead.c
> @@ -24,6 +24,7 @@
> #include <linux/slab.h>
> #include <linux/seq_file.h>
> #include <linux/cryptouser.h>
> +#include <linux/compiler.h>
> #include <net/netlink.h>
>
> #include "internal.h"
> @@ -132,7 +133,7 @@ static int crypto_aead_report(struct sk_buff *skb, struct crypto_alg *alg)
> #endif
>
> static void crypto_aead_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
> static void crypto_aead_show(struct seq_file *m, struct crypto_alg *alg)
> {
> struct aead_alg *aead = container_of(alg, struct aead_alg, base);
> diff --git a/crypto/ahash.c b/crypto/ahash.c
> index 2ce8bcb..e58c497 100644
> --- a/crypto/ahash.c
> +++ b/crypto/ahash.c
> @@ -23,6 +23,7 @@
> #include <linux/slab.h>
> #include <linux/seq_file.h>
> #include <linux/cryptouser.h>
> +#include <linux/compiler.h>
> #include <net/netlink.h>
>
> #include "internal.h"
> @@ -493,7 +494,7 @@ static int crypto_ahash_report(struct sk_buff *skb, struct crypto_alg *alg)
> #endif
>
> static void crypto_ahash_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
> static void crypto_ahash_show(struct seq_file *m, struct crypto_alg *alg)
> {
> seq_printf(m, "type : ahash\n");
> diff --git a/crypto/akcipher.c b/crypto/akcipher.c
> index def301e..cfbdb06 100644
> --- a/crypto/akcipher.c
> +++ b/crypto/akcipher.c
> @@ -17,6 +17,7 @@
> #include <linux/slab.h>
> #include <linux/string.h>
> #include <linux/crypto.h>
> +#include <linux/compiler.h>
> #include <crypto/algapi.h>
> #include <linux/cryptouser.h>
> #include <net/netlink.h>
> @@ -47,7 +48,7 @@ static int crypto_akcipher_report(struct sk_buff *skb, struct crypto_alg *alg)
> #endif
>
> static void crypto_akcipher_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
>
> static void crypto_akcipher_show(struct seq_file *m, struct crypto_alg *alg)
> {
> diff --git a/crypto/blkcipher.c b/crypto/blkcipher.c
> index a832426..6c43a0a 100644
> --- a/crypto/blkcipher.c
> +++ b/crypto/blkcipher.c
> @@ -1,6 +1,6 @@
> /*
> * Block chaining cipher operations.
> - *
> + *
> * Generic encrypt/decrypt wrapper for ciphers, handles operations across
> * multiple page boundaries by using temporary blocks. In user context,
> * the kernel is given a chance to schedule us once per page.
> @@ -9,7 +9,7 @@
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms of the GNU General Public License as published by the Free
> - * Software Foundation; either version 2 of the License, or (at your option)
> + * Software Foundation; either version 2 of the License, or (at your option)
> * any later version.
> *
> */
> @@ -25,6 +25,7 @@
> #include <linux/slab.h>
> #include <linux/string.h>
> #include <linux/cryptouser.h>
> +#include <linux/compiler.h>
> #include <net/netlink.h>
>
> #include "internal.h"
> @@ -534,7 +535,7 @@ static int crypto_blkcipher_report(struct sk_buff *skb, struct crypto_alg *alg)
> #endif
>
> static void crypto_blkcipher_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
> static void crypto_blkcipher_show(struct seq_file *m, struct crypto_alg *alg)
> {
> seq_printf(m, "type : blkcipher\n");
> diff --git a/crypto/cts.c b/crypto/cts.c
> index 00254d7..a1335d6 100644
> --- a/crypto/cts.c
> +++ b/crypto/cts.c
> @@ -49,6 +49,7 @@
> #include <linux/scatterlist.h>
> #include <crypto/scatterwalk.h>
> #include <linux/slab.h>
> +#include <linux/compiler.h>
>
> struct crypto_cts_ctx {
> struct crypto_skcipher *child;
> @@ -103,7 +104,7 @@ static int cts_cbc_encrypt(struct skcipher_request *req)
> struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
> struct skcipher_request *subreq = &rctx->subreq;
> int bsize = crypto_skcipher_blocksize(tfm);
> - u8 d[bsize * 2] __attribute__ ((aligned(__alignof__(u32))));
> + u8 d[bsize * 2] __aligned(__alignof__(u32));
> struct scatterlist *sg;
> unsigned int offset;
> int lastn;
> @@ -183,7 +184,7 @@ static int cts_cbc_decrypt(struct skcipher_request *req)
> struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
> struct skcipher_request *subreq = &rctx->subreq;
> int bsize = crypto_skcipher_blocksize(tfm);
> - u8 d[bsize * 2] __attribute__ ((aligned(__alignof__(u32))));
> + u8 d[bsize * 2] __aligned(__alignof__(u32));
> struct scatterlist *sg;
> unsigned int offset;
> u8 *space;
> diff --git a/crypto/kpp.c b/crypto/kpp.c
> index d36ce05..a90edc2 100644
> --- a/crypto/kpp.c
> +++ b/crypto/kpp.c
> @@ -19,6 +19,7 @@
> #include <linux/crypto.h>
> #include <crypto/algapi.h>
> #include <linux/cryptouser.h>
> +#include <linux/compiler.h>
> #include <net/netlink.h>
> #include <crypto/kpp.h>
> #include <crypto/internal/kpp.h>
> @@ -47,7 +48,7 @@ static int crypto_kpp_report(struct sk_buff *skb, struct crypto_alg *alg)
> #endif
>
> static void crypto_kpp_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
>
> static void crypto_kpp_show(struct seq_file *m, struct crypto_alg *alg)
> {
> diff --git a/crypto/pcbc.c b/crypto/pcbc.c
> index e4538e0..11d2486 100644
> --- a/crypto/pcbc.c
> +++ b/crypto/pcbc.c
> @@ -20,6 +20,7 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/slab.h>
> +#include <linux/compiler.h>
>
> struct crypto_pcbc_ctx {
> struct crypto_cipher *child;
> @@ -146,7 +147,7 @@ static int crypto_pcbc_decrypt_inplace(struct skcipher_request *req,
> unsigned int nbytes = walk->nbytes;
> u8 *src = walk->src.virt.addr;
> u8 *iv = walk->iv;
> - u8 tmpbuf[bsize] __attribute__ ((aligned(__alignof__(u32))));
> + u8 tmpbuf[bsize] __aligned(__alignof__(u32));
>
> do {
> memcpy(tmpbuf, src, bsize);
> diff --git a/crypto/rng.c b/crypto/rng.c
> index b81cffb..f46dac5 100644
> --- a/crypto/rng.c
> +++ b/crypto/rng.c
> @@ -23,6 +23,7 @@
> #include <linux/slab.h>
> #include <linux/string.h>
> #include <linux/cryptouser.h>
> +#include <linux/compiler.h>
> #include <net/netlink.h>
>
> #include "internal.h"
> @@ -95,7 +96,7 @@ static int crypto_rng_report(struct sk_buff *skb, struct crypto_alg *alg)
> #endif
>
> static void crypto_rng_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
> static void crypto_rng_show(struct seq_file *m, struct crypto_alg *alg)
> {
> seq_printf(m, "type : rng\n");
> diff --git a/crypto/scompress.c b/crypto/scompress.c
> index 35e396d..6b048b3 100644
> --- a/crypto/scompress.c
> +++ b/crypto/scompress.c
> @@ -18,6 +18,7 @@
> #include <linux/slab.h>
> #include <linux/string.h>
> #include <linux/crypto.h>
> +#include <linux/compiler.h>
> #include <linux/vmalloc.h>
> #include <crypto/algapi.h>
> #include <linux/cryptouser.h>
> @@ -57,7 +58,7 @@ static int crypto_scomp_report(struct sk_buff *skb, struct crypto_alg *alg)
> #endif
>
> static void crypto_scomp_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
>
> static void crypto_scomp_show(struct seq_file *m, struct crypto_alg *alg)
> {
> diff --git a/crypto/shash.c b/crypto/shash.c
> index a051541..5e31c8d 100644
> --- a/crypto/shash.c
> +++ b/crypto/shash.c
> @@ -19,6 +19,7 @@
> #include <linux/seq_file.h>
> #include <linux/cryptouser.h>
> #include <net/netlink.h>
> +#include <linux/compiler.h>
>
> #include "internal.h"
>
> @@ -67,7 +68,7 @@ EXPORT_SYMBOL_GPL(crypto_shash_setkey);
> static inline unsigned int shash_align_buffer_size(unsigned len,
> unsigned long mask)
> {
> - typedef u8 __attribute__ ((aligned)) u8_aligned;
> + typedef u8 __aligned_largest u8_aligned;
> return len + (mask & ~(__alignof__(u8_aligned) - 1));
> }
>
> @@ -80,7 +81,7 @@ static int shash_update_unaligned(struct shash_desc *desc, const u8 *data,
> unsigned int unaligned_len = alignmask + 1 -
> ((unsigned long)data & alignmask);
> u8 ubuf[shash_align_buffer_size(unaligned_len, alignmask)]
> - __attribute__ ((aligned));
> + __aligned_largest;
> u8 *buf = PTR_ALIGN(&ubuf[0], alignmask + 1);
> int err;
>
> @@ -116,7 +117,7 @@ static int shash_final_unaligned(struct shash_desc *desc, u8 *out)
> struct shash_alg *shash = crypto_shash_alg(tfm);
> unsigned int ds = crypto_shash_digestsize(tfm);
> u8 ubuf[shash_align_buffer_size(ds, alignmask)]
> - __attribute__ ((aligned));
> + __aligned_largest;
> u8 *buf = PTR_ALIGN(&ubuf[0], alignmask + 1);
> int err;
>
> @@ -403,7 +404,7 @@ static int crypto_shash_report(struct sk_buff *skb, struct crypto_alg *alg)
> #endif
>
> static void crypto_shash_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
> static void crypto_shash_show(struct seq_file *m, struct crypto_alg *alg)
> {
> struct shash_alg *salg = __crypto_shash_alg(alg);
> diff --git a/crypto/skcipher.c b/crypto/skcipher.c
> index 0e1e6c3..1a0bd92 100644
> --- a/crypto/skcipher.c
> +++ b/crypto/skcipher.c
> @@ -19,6 +19,7 @@
> #include <crypto/scatterwalk.h>
> #include <linux/bug.h>
> #include <linux/cryptouser.h>
> +#include <linux/compiler.h>
> #include <linux/list.h>
> #include <linux/module.h>
> #include <linux/rtnetlink.h>
> @@ -807,7 +808,7 @@ static void crypto_skcipher_free_instance(struct crypto_instance *inst)
> }
>
> static void crypto_skcipher_show(struct seq_file *m, struct crypto_alg *alg)
> - __attribute__ ((unused));
> + __maybe_unused;
> static void crypto_skcipher_show(struct seq_file *m, struct crypto_alg *alg)
> {
> struct skcipher_alg *skcipher = container_of(alg, struct skcipher_alg,
> diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
> index 0444b13..fddd1a5 100644
> --- a/include/linux/compiler-gcc.h
> +++ b/include/linux/compiler-gcc.h
> @@ -116,6 +116,7 @@
> */
> #define __pure __attribute__((pure))
> #define __aligned(x) __attribute__((aligned(x)))
> +#define __aligned_largest __attribute__((aligned))
> #define __printf(a, b) __attribute__((format(printf, a, b)))
> #define __scanf(a, b) __attribute__((format(scanf, a, b)))
> #define __attribute_const__ __attribute__((__const__))
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH] crypto: arm64/aes - add scalar implementation
From: Ard Biesheuvel @ 2017-01-04 16:19 UTC (permalink / raw)
To: linux-crypto, linux-arm-kernel; +Cc: herbert, Ard Biesheuvel
This adds a scalar implementation of AES, based on the precomputed tables
that are exposed by the generic AES code. Since rotates are cheap on arm64,
this implementation only uses the 4 core tables (of 1 KB each), and avoids
the prerotated ones, reducing the D-cache footprint by 75%.
On Cortex-A57, this code manages 13.0 cycles per byte, which is ~34% faster
than the generic C code. (Note that this is still >13x slower than the code
that uses the optional ARMv8 Crypto Extensions, which manages <1 cycles per
byte.)
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Raw performance data after the patch, which was generated on a 2 GHz
Cortex-A57 (AMD Seattle B1).
arch/arm64/crypto/Kconfig | 4 +
arch/arm64/crypto/Makefile | 3 +
arch/arm64/crypto/aes-cipher-core.S | 126 ++++++++++++++++++++
arch/arm64/crypto/aes-cipher-glue.c | 69 +++++++++++
4 files changed, 202 insertions(+)
diff --git a/arch/arm64/crypto/Kconfig b/arch/arm64/crypto/Kconfig
index 0bf0f531f539..0826f8e599a6 100644
--- a/arch/arm64/crypto/Kconfig
+++ b/arch/arm64/crypto/Kconfig
@@ -41,6 +41,10 @@ config CRYPTO_CRC32_ARM64_CE
depends on KERNEL_MODE_NEON && CRC32
select CRYPTO_HASH
+config CRYPTO_AES_ARM64
+ tristate "AES core cipher using scalar instructions"
+ select CRYPTO_AES
+
config CRYPTO_AES_ARM64_CE
tristate "AES core cipher using ARMv8 Crypto Extensions"
depends on ARM64 && KERNEL_MODE_NEON
diff --git a/arch/arm64/crypto/Makefile b/arch/arm64/crypto/Makefile
index 9d2826c5fccf..a893507629eb 100644
--- a/arch/arm64/crypto/Makefile
+++ b/arch/arm64/crypto/Makefile
@@ -44,6 +44,9 @@ sha512-arm64-y := sha512-glue.o sha512-core.o
obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha20-neon.o
chacha20-neon-y := chacha20-neon-core.o chacha20-neon-glue.o
+obj-$(CONFIG_CRYPTO_AES_ARM64) += aes-arm64.o
+aes-arm64-y := aes-cipher-core.o aes-cipher-glue.o
+
AFLAGS_aes-ce.o := -DINTERLEAVE=4
AFLAGS_aes-neon.o := -DINTERLEAVE=4
diff --git a/arch/arm64/crypto/aes-cipher-core.S b/arch/arm64/crypto/aes-cipher-core.S
new file mode 100644
index 000000000000..22d1bc46feba
--- /dev/null
+++ b/arch/arm64/crypto/aes-cipher-core.S
@@ -0,0 +1,126 @@
+/*
+ * Scalar AES core transform
+ *
+ * Copyright (C) 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ .text
+ .align 5
+
+ rk .req x0
+ out .req x1
+ in .req x2
+ rounds .req x3
+ tt .req x4
+ lt .req x2
+
+ .macro __hround, out0, out1, in0, in1, in2, in3, t0, t1, enc
+ ldp \out0, \out1, [rk], #8
+
+ ubfx w13, \in0, #0, #8
+ ubfx w14, \in1, #8, #8
+ ldr w13, [tt, w13, uxtw #2]
+ ldr w14, [tt, w14, uxtw #2]
+
+ ubfx w15, \in2, #16, #8
+ ubfx w16, \in3, #24, #8
+ ldr w15, [tt, w15, uxtw #2]
+ ldr w16, [tt, w16, uxtw #2]
+
+ .if \enc
+ ubfx w17, \in1, #0, #8
+ ubfx w18, \in2, #8, #8
+ .else
+ ubfx w17, \in3, #0, #8
+ ubfx w18, \in0, #8, #8
+ .endif
+ ldr w17, [tt, w17, uxtw #2]
+ ldr w18, [tt, w18, uxtw #2]
+
+ .if \enc
+ ubfx \t0, \in3, #16, #8
+ ubfx \t1, \in0, #24, #8
+ .else
+ ubfx \t0, \in1, #16, #8
+ ubfx \t1, \in2, #24, #8
+ .endif
+ ldr \t0, [tt, \t0, uxtw #2]
+ ldr \t1, [tt, \t1, uxtw #2]
+
+ eor \out0, \out0, w13
+ eor \out1, \out1, w17
+ eor \out0, \out0, w14, ror #24
+ eor \out1, \out1, w18, ror #24
+ eor \out0, \out0, w15, ror #16
+ eor \out1, \out1, \t0, ror #16
+ eor \out0, \out0, w16, ror #8
+ eor \out1, \out1, \t1, ror #8
+ .endm
+
+ .macro fround, out0, out1, out2, out3, in0, in1, in2, in3
+ __hround \out0, \out1, \in0, \in1, \in2, \in3, \out2, \out3, 1
+ __hround \out2, \out3, \in2, \in3, \in0, \in1, \in1, \in2, 1
+ .endm
+
+ .macro iround, out0, out1, out2, out3, in0, in1, in2, in3
+ __hround \out0, \out1, \in0, \in3, \in2, \in1, \out2, \out3, 0
+ __hround \out2, \out3, \in2, \in1, \in0, \in3, \in1, \in0, 0
+ .endm
+
+ .macro do_crypt, round, ttab, ltab
+ ldp w5, w6, [in]
+ ldp w7, w8, [in, #8]
+ ldp w9, w10, [rk], #16
+ ldp w11, w12, [rk, #-8]
+
+CPU_BE( rev w5, w5 )
+CPU_BE( rev w6, w6 )
+CPU_BE( rev w7, w7 )
+CPU_BE( rev w8, w8 )
+
+ eor w5, w5, w9
+ eor w6, w6, w10
+ eor w7, w7, w11
+ eor w8, w8, w12
+
+ ldr tt, =\ttab
+ ldr lt, =\ltab
+
+ tbnz rounds, #1, 1f
+
+0: \round w9, w10, w11, w12, w5, w6, w7, w8
+ \round w5, w6, w7, w8, w9, w10, w11, w12
+
+1: subs rounds, rounds, #4
+ \round w9, w10, w11, w12, w5, w6, w7, w8
+ csel tt, tt, lt, hi
+ \round w5, w6, w7, w8, w9, w10, w11, w12
+ b.hi 0b
+
+CPU_BE( rev w5, w5 )
+CPU_BE( rev w6, w6 )
+CPU_BE( rev w7, w7 )
+CPU_BE( rev w8, w8 )
+
+ stp w5, w6, [out]
+ stp w7, w8, [out, #8]
+ ret
+
+ .align 4
+ .ltorg
+ .endm
+
+ENTRY(__aes_arm64_encrypt)
+ do_crypt fround, crypto_ft_tab, crypto_fl_tab
+ENDPROC(__aes_arm64_encrypt)
+
+ENTRY(__aes_arm64_decrypt)
+ do_crypt iround, crypto_it_tab, crypto_il_tab
+ENDPROC(__aes_arm64_decrypt)
diff --git a/arch/arm64/crypto/aes-cipher-glue.c b/arch/arm64/crypto/aes-cipher-glue.c
new file mode 100644
index 000000000000..7288e7cbebff
--- /dev/null
+++ b/arch/arm64/crypto/aes-cipher-glue.c
@@ -0,0 +1,69 @@
+/*
+ * Scalar AES core transform
+ *
+ * Copyright (C) 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <crypto/aes.h>
+#include <linux/crypto.h>
+#include <linux/module.h>
+
+asmlinkage void __aes_arm64_encrypt(u32 *rk, u8 *out, const u8 *in, int rounds);
+EXPORT_SYMBOL(__aes_arm64_encrypt);
+
+asmlinkage void __aes_arm64_decrypt(u32 *rk, u8 *out, const u8 *in, int rounds);
+EXPORT_SYMBOL(__aes_arm64_decrypt);
+
+static void aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+ struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+ int rounds = 6 + ctx->key_length / 4;
+
+ __aes_arm64_encrypt(ctx->key_enc, out, in, rounds);
+}
+
+static void aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+ struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+ int rounds = 6 + ctx->key_length / 4;
+
+ __aes_arm64_decrypt(ctx->key_dec, out, in, rounds);
+}
+
+static struct crypto_alg aes_alg = {
+ .cra_name = "aes",
+ .cra_driver_name = "aes-arm64",
+ .cra_priority = 200,
+ .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct crypto_aes_ctx),
+ .cra_module = THIS_MODULE,
+
+ .cra_cipher.cia_min_keysize = AES_MIN_KEY_SIZE,
+ .cra_cipher.cia_max_keysize = AES_MAX_KEY_SIZE,
+ .cra_cipher.cia_setkey = crypto_aes_set_key,
+ .cra_cipher.cia_encrypt = aes_encrypt,
+ .cra_cipher.cia_decrypt = aes_decrypt
+};
+
+static int __init aes_init(void)
+{
+ return crypto_register_alg(&aes_alg);
+}
+
+static void __exit aes_fini(void)
+{
+ crypto_unregister_alg(&aes_alg);
+}
+
+module_init(aes_init);
+module_exit(aes_fini);
+
+MODULE_DESCRIPTION("Scalar AES cipher for arm64");
+MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS_CRYPTO("aes");
--
2.7.4
testing speed of async ecb(aes) (ecb(aes-generic)) encryption
test 0 (128 bit key, 16 byte blocks): 4594689 operations in 1 seconds (73515024 bytes)
test 1 (128 bit key, 64 byte blocks): 1585137 operations in 1 seconds (101448768 bytes)
test 2 (128 bit key, 256 byte blocks): 435173 operations in 1 seconds (111404288 bytes)
test 3 (128 bit key, 1024 byte blocks): 111505 operations in 1 seconds (114181120 bytes)
test 4 (128 bit key, 8192 byte blocks): 14093 operations in 1 seconds (115449856 bytes)
test 5 (192 bit key, 16 byte blocks): 4078345 operations in 1 seconds (65253520 bytes)
test 6 (192 bit key, 64 byte blocks): 1349425 operations in 1 seconds (86363200 bytes)
test 7 (192 bit key, 256 byte blocks): 365631 operations in 1 seconds (93601536 bytes)
test 8 (192 bit key, 1024 byte blocks): 93362 operations in 1 seconds (95602688 bytes)
test 9 (192 bit key, 8192 byte blocks): 11729 operations in 1 seconds (96083968 bytes)
test 10 (256 bit key, 16 byte blocks): 3692945 operations in 1 seconds (59087120 bytes)
test 11 (256 bit key, 64 byte blocks): 1182522 operations in 1 seconds (75681408 bytes)
test 12 (256 bit key, 256 byte blocks): 317285 operations in 1 seconds (81224960 bytes)
test 13 (256 bit key, 1024 byte blocks): 80459 operations in 1 seconds (82390016 bytes)
test 14 (256 bit key, 8192 byte blocks): 10138 operations in 1 seconds (83050496 bytes)
testing speed of async ecb(aes) (ecb(aes-arm64)) encryption
test 0 (128 bit key, 16 byte blocks): 5455304 operations in 1 seconds (87284864 bytes)
test 1 (128 bit key, 64 byte blocks): 2000321 operations in 1 seconds (128020544 bytes)
test 2 (128 bit key, 256 byte blocks): 574174 operations in 1 seconds (146988544 bytes)
test 3 (128 bit key, 1024 byte blocks): 148497 operations in 1 seconds (152060928 bytes)
test 4 (128 bit key, 8192 byte blocks): 18836 operations in 1 seconds (154304512 bytes)
test 5 (192 bit key, 16 byte blocks): 4962478 operations in 1 seconds (79399648 bytes)
test 6 (192 bit key, 64 byte blocks): 1740157 operations in 1 seconds (111370048 bytes)
test 7 (192 bit key, 256 byte blocks): 490443 operations in 1 seconds (125553408 bytes)
test 8 (192 bit key, 1024 byte blocks): 126165 operations in 1 seconds (129192960 bytes)
test 9 (192 bit key, 8192 byte blocks): 15897 operations in 1 seconds (130228224 bytes)
test 10 (256 bit key, 16 byte blocks): 4527784 operations in 1 seconds (72444544 bytes)
test 11 (256 bit key, 64 byte blocks): 1527235 operations in 1 seconds (97743040 bytes)
test 12 (256 bit key, 256 byte blocks): 425302 operations in 1 seconds (108877312 bytes)
test 13 (256 bit key, 1024 byte blocks): 109013 operations in 1 seconds (111629312 bytes)
test 14 (256 bit key, 8192 byte blocks): 13778 operations in 1 seconds (112869376 bytes)
^ permalink raw reply related
* Re: [PATCH 1/5] ARM: wire up HWCAP2 feature bits to the CPU modalias
From: Ard Biesheuvel @ 2017-01-04 16:42 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: linux-arm-kernel@lists.infradead.org,
linux-crypto@vger.kernel.org, Herbert Xu, Steve Capper
In-Reply-To: <20170102234013.GK14217@n2100.armlinux.org.uk>
On 2 January 2017 at 23:40, Russell King - ARM Linux
<linux@armlinux.org.uk> wrote:
> On Mon, Jan 02, 2017 at 09:06:04PM +0000, Ard Biesheuvel wrote:
>> On 31 October 2016 at 16:13, Russell King - ARM Linux
>> <linux@armlinux.org.uk> wrote:
>> > On Sat, Oct 29, 2016 at 11:08:36AM +0100, Ard Biesheuvel wrote:
>> >> On 18 October 2016 at 11:52, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>> >> > Wire up the generic support for exposing CPU feature bits via the
>> >> > modalias in /sys/device/system/cpu. This allows udev to automatically
>> >> > load modules for things like crypto algorithms that are implemented
>> >> > using optional instructions.
>> >> >
>> >> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> >> > ---
>> >> > arch/arm/Kconfig | 1 +
>> >> > arch/arm/include/asm/cpufeature.h | 32 ++++++++++++++++++++
>> >> > 2 files changed, 33 insertions(+)
>> >> >
>> >>
>> >> Russell,
>> >>
>> >> do you have any concerns regarding this patch? If not, I will drop it
>> >> into the patch system.
>> >
>> > It's still something I need to look at... I've been offline last week,
>> > and sort-of offline the previous week, so I'm catching up.
>> >
>>
>> Hi Russell,
>>
>> Any thoughts yet?
>
> None, and the patch is well buried now that it'll take me a while to
> find... back in mid-October? Yea, I'll have to drop everything and
> go digging through my mailboxes to find it... and I'm just catching
> up (again) after a week and a bit's time offline - yep, it's wonderful
> timing. Sorry, no time to look at it right now, you're not the only
> one wanting my attention at the moment.
>
No worries. It is not exactly urgent, but it is a useful enhancement
nonetheless.
> Please try again in about a week's time - don't leave it a few months,
> and please include the patch.
>
OK
^ permalink raw reply
* Re: console noise after commit c1e9b3b0eea
From: Shannon Nelson @ 2017-01-05 0:44 UTC (permalink / raw)
To: Anatoly Pugachev; +Cc: SOWMINI.VARADHAN, sparclinux, linux-crypto
In-Reply-To: <a0a9e8ae-38a8-9bb8-d3b7-2f4b50809096@oracle.com>
Resurrecting an old thread, pulled out of
http://www.spinics.net/lists/linux-crypto/msg19192.html
On Wed, Apr 20, 2016 at 9:18 AM, Anatoly Pugachev <matorola@xxxxxxxxx>
wrote:
> On Wed, Apr 20, 2016 at 1:33 AM, Sowmini Varadhan
> <sowmini.varadhan@xxxxxxxxxx> wrote:
>>
>> Hi Anatoly,
>>
>> after commit c1e9b3b0eea1 ("hwrng: n2 - Attach on T5/M5, T7/M7 SPARC
> CPUs")
>> I get a *lot* of console noise on my T5-2, of the form:
>>
>> n2rng f028f21c: Selftest failed on unit 0
>> n2rng f028f21c: Test buffer slot 0 [0x0000000000000000]
>> n2rng f028f21c: Test buffer slot 1 [0xe63f56d6a22eb116]
>> n2rng f028f21c: Test buffer slot 2 [0xe63f56d6a22eb116]
>> n2rng f028f21c: Test buffer slot 3 [0xe63f56d6a22eb116]
>> n2rng f028f21c: Test buffer slot 4 [0xe63f56d6a22eb116]
>> n2rng f028f21c: Test buffer slot 5 [0xe63f56d6a22eb116]
>> n2rng f028f21c: Test buffer slot 6 [0xe63f56d6a22eb116]
>> n2rng f028f21c: Test buffer slot 7 [0xe63f56d6a22eb116]
>>
>> Why/when is your commit needed on my T5-2?
>>
>> I'm not sure how this was tested, but if you need to revise it and test
>> on sparc, please let me know- I think it needs more work on sparc.
>
> Sowmini,
>
> the patch/commit is actually quite trivial, it just adds device_id
> matches for newer T5/M7 CPUs to n2rng_match structure. Without this
> patch, n2rng does not work on this newer CPUs. Works well on my T5-2
> LDOM (tested with rng-tools and gpg --gen-key). I don't have M7
^^^^
Anatoly, I think your LDOM is why you don't see the problem. Yes, your
patch works just fine when running in a client LDOM, but we see a
problem when running this on sparc "bare metal". Did you test this on
the bare metal so that the self-test would run?
It seems there's an issue with the self-test in the newer hardware and
the driver will never stop trying to retest the hardware. I'm
contemplating a patch to limit the self-test attempts, at least until we
can figure out what is the root of the issue.
sln
> machine to test it with.
>
> Why the n2rng selftest fails on your machine - I've no idea... Just to
> silence it, you can blacklist this module, since it does not work your
> hardware anyway.
>
> Can you please send me "prtconf -pv" output from your machine, as well
> information on how do you run linux as LDOM container or baremetal
> T5-2 ?
>
> Mine T5-2 is one of the last firmware releases (run from solaris 11.3
> control domain):
>
> root@deimos:/home/sysadmin# prtdiag -v
> ============================ FW Version ============================
> Sun System Firmware 9.5.3 2015/11/25 09:50
>
> sysadmin@deimos:~$ ldm -V
>
> Logical Domains Manager (v 3.3.0.0.17)
> Hypervisor control protocol v 1.12
> Using Hypervisor MD v 1.4
>
> System PROM:
> Hostconfig v. 1.6.3 @(#)Hostconfig 1.6.3 2015/11/25
> 08:57
> Hypervisor v. 1.15.3 @(#)Hypervisor 1.15.3 2015/11/11
> 17:15
> OpenBoot v. 4.38.3 @(#)OpenBoot 4.38.3 2015/11/11
> 10:38
>
>
> Can you please check what firmware release if yours T5-2 server and
> probably update? I'm not sure it would help, but anyway.
>
>
>
^ permalink raw reply
* Re: [RFC PATCH v2] crypto: Add IV generation algorithms
From: Binoy Jayan @ 2017-01-05 6:06 UTC (permalink / raw)
To: Herbert Xu
Cc: Milan Broz, Oded, Ofir, David S. Miller, linux-crypto, Mark Brown,
Arnd Bergmann, Linux kernel mailing list, Alasdair Kergon,
Mike Snitzer, dm-devel, Shaohua Li, linux-raid, Rajendra
In-Reply-To: <20170102065325.GA19553@gondor.apana.org.au>
Hi Herbert,
On 2 January 2017 at 12:23, Herbert Xu <herbert@gondor.apana.org.au> wrote:
> On Mon, Jan 02, 2017 at 12:16:45PM +0530, Binoy Jayan wrote:
>
> Right. The actual number of underlying tfms that do the work
> won't change compared to the status quo. We're just structuring
> it such that if the overall scheme is supported by the hardware
> then we can feed more than one sector at a time to it.
I was thinking of continuing to have the iv generation algorithms as template
ciphers instead of regular 'skcipher' as it is easier to inherit the parameters
from the underlying cipher (e.g. aes) like cra_blocksize, cra_alignmask,
ivsize, chunksize etc.
Usually, the underlying cipher for the template ciphers are instantiated
in the following function:
skcipher_instance:skcipher_alg:init()
Since the number of such cipher instances depend on the key count, which is
not known at the time of creation of the cipher (it's passed to as an argument
to the setkey api), the creation of those have to be delayed until the setkey
operation of the template cipher. But as Mark pointed out, the users of this
cipher may get confused if the creation of the underlying cipher fails while
trying to do a 'setkey' on the template cipher. I was wondering if I can create
a single instance of the cipher and assign it to tfms[0] and allocate the
remaining instances when the setkey operation is called later with the encoded
key_count so that errors during cipher creation are uncovered earlier.
Thanks,
Binoy
^ permalink raw reply
* Re: [PATCH v3 1/3] drivers: crypto: Add Support for Octeon-tx CPT Engine
From: George Cherian @ 2017-01-06 6:19 UTC (permalink / raw)
To: Corentin Labbe, george.cherian
Cc: herbert, davem, linux-kernel, linux-crypto, david.daney
In-Reply-To: <20161221132347.GA21051@Red>
Hi Corentin,
Thank you very much for the review.
I was on vacation and now am back, I will fix your comments and send a
new version.
On 12/21/2016 06:53 PM, Corentin Labbe wrote:
> Hello
>
> I have some comment inline
>
> On Wed, Dec 21, 2016 at 11:56:11AM +0000, george.cherian@cavium.com wrote:
>> From: George Cherian <george.cherian@cavium.com>
>>
>> Enable the Physical Function diver for the Cavium Crypto Engine (CPT)
>
> typo driver
okay
>
>> found in Octeon-tx series of SoC's. CPT is the Cryptographic Acceleration
>> Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
>> asymmetric engines (AEs).
>>
>> Signed-off-by: George Cherian <george.cherian@cavium.com>
>> Reviewed-by: David Daney <david.daney@cavium.com>
>> ---
>> drivers/crypto/cavium/cpt/Kconfig | 16 +
>> drivers/crypto/cavium/cpt/Makefile | 2 +
>> drivers/crypto/cavium/cpt/cpt_common.h | 158 +++++++
>> drivers/crypto/cavium/cpt/cpt_hw_types.h | 658 +++++++++++++++++++++++++++++
>> drivers/crypto/cavium/cpt/cptpf.h | 69 +++
>> drivers/crypto/cavium/cpt/cptpf_main.c | 703 +++++++++++++++++++++++++++++++
>> drivers/crypto/cavium/cpt/cptpf_mbox.c | 163 +++++++
>> 7 files changed, 1769 insertions(+)
>> create mode 100644 drivers/crypto/cavium/cpt/Kconfig
>> create mode 100644 drivers/crypto/cavium/cpt/Makefile
>> create mode 100644 drivers/crypto/cavium/cpt/cpt_common.h
>> create mode 100644 drivers/crypto/cavium/cpt/cpt_hw_types.h
>> create mode 100644 drivers/crypto/cavium/cpt/cptpf.h
>> create mode 100644 drivers/crypto/cavium/cpt/cptpf_main.c
>> create mode 100644 drivers/crypto/cavium/cpt/cptpf_mbox.c
>>
>> diff --git a/drivers/crypto/cavium/cpt/Kconfig b/drivers/crypto/cavium/cpt/Kconfig
>> new file mode 100644
>> index 0000000..247f1cb
>> --- /dev/null
>> +++ b/drivers/crypto/cavium/cpt/Kconfig
>> @@ -0,0 +1,16 @@
>> +#
>> +# Cavium crypto device configuration
>> +#
>> +
>> +config CRYPTO_DEV_CPT
>> + tristate
>> +
>> +config CAVIUM_CPT
>> + tristate "Cavium Cryptographic Accelerator driver"
>> + depends on ARCH_THUNDER
>> + select CRYPTO_DEV_CPT
>
> Could you add some COMPILE_TEST ?
You meant depends on ARCH_THUNDER || COMPILE_TEST?
>
> [...]
>> +struct microcode {
>> + u8 is_mc_valid;
>> + u8 is_ae;
>> + u8 group;
>> + u8 num_cores;
>> + u32 code_size;
>> + u64 core_mask;
>> + u8 version[32];
>
> I see this "32" in some other place, perhaps you could use a define
okay
>
> [...]
>> +#include <linux/version.h>
>> +#include <linux/module.h>
>> +#include <linux/moduleparam.h>
>> +#include <linux/printk.h>
>> +#include <linux/device.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/firmware.h>
>> +#include <linux/pci.h>
>
> Header need to be sorted
will do
>
> [...]
>> +static void cpt_disable_cores(struct cpt_device *cpt, u64 coremask,
>> + u8 type, u8 grp)
>> +{
>> + u64 pf_exe_ctl;
>> + u32 timeout = 0xFFFFFFFF;
>> + u64 grpmask = 0;
>> + struct device *dev = &cpt->pdev->dev;
>> +
>> + if (type == AE_TYPES)
>> + coremask = (coremask << cpt->max_se_cores);
>> +
>> + /* Disengage the cores from groups */
>> + grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));
>> + cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp),
>> + (grpmask & ~coremask));
>> + udelay(CSR_DELAY);
>> + grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0));
>> + while (grp & coremask) {
>> + dev_err(dev, "Cores still busy %llx", coremask);
>> + grp = cpt_read_csr64(cpt->reg_base,
>> + CPTX_PF_EXEC_BUSY(0));
>> + if (timeout--)
>> + break;
>
> The timeout seems enormous and you will flooding syslog with dev_err()
will reduce.
>
>> + }
>> +
>> + /* Disable the cores */
>> + pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0));
>> + cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0),
>> + (pf_exe_ctl & ~coremask));
>> + udelay(CSR_DELAY);
>> +}
>> +
>> +/*
>> + * Enable cores specified by coremask
>> + */
>> +static void cpt_enable_cores(struct cpt_device *cpt, u64 coremask,
>> + u8 type)
>> +{
>> + u64 pf_exe_ctl;
>> +
>> + if (type == AE_TYPES)
>> + coremask = (coremask << cpt->max_se_cores);
>> +
>> + pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0));
>> + cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0),
>> + (pf_exe_ctl | coremask));
>> + udelay(CSR_DELAY);
>> +}
>> +
>> +static void cpt_configure_group(struct cpt_device *cpt, u8 grp,
>> + u64 coremask, u8 type)
>> +{
>> + u64 pf_gx_en = 0;
>> +
>> + if (type == AE_TYPES)
>> + coremask = (coremask << cpt->max_se_cores);
>> +
>> + pf_gx_en = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp));
>> + cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp),
>> + (pf_gx_en | coremask));
>> + udelay(CSR_DELAY);
>> +}
>> +
>> +static void cpt_disable_mbox_interrupts(struct cpt_device *cpt)
>> +{
>> + /* Clear mbox(0) interupts for all vfs */
>> + cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull);
>> +}
>> +
>> +static void cpt_disable_ecc_interrupts(struct cpt_device *cpt)
>> +{
>> + /* Clear ecc(0) interupts for all vfs */
>> + cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull);
>> +}
>> +
>> +static void cpt_disable_exec_interrupts(struct cpt_device *cpt)
>> +{
>> + /* Clear exec interupts for all vfs */
>> + cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull);
>> +}
>> +
>> +static void cpt_disable_all_interrupts(struct cpt_device *cpt)
>> +{
>> + cpt_disable_mbox_interrupts(cpt);
>> + cpt_disable_ecc_interrupts(cpt);
>> + cpt_disable_exec_interrupts(cpt);
>> +}
>> +
>> +static void cpt_enable_mbox_interrupts(struct cpt_device *cpt)
>> +{
>> + /* Set mbox(0) interupts for all vfs */
>> + cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull);
>> +}
>> +
>> +static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode)
>> +{
>> + int ret = 0, core = 0, shift = 0;
>> + u32 total_cores = 0;
>> + struct device *dev = &cpt->pdev->dev;
>> +
>> + if (!mcode || !mcode->code) {
>> + dev_err(dev, "Either the mcode is null or data is NULL\n");
>> + return 1;
>
> This is not a standard error code
>
Yes will return standard error codes.
>> + }
>> +
>> + if (mcode->code_size == 0) {
>> + dev_err(dev, "microcode size is 0\n");
>> + return 1;
>
> the same
>
>> + }
>> +
>> + /* Assumes 0-9 are SE cores for UCODE_BASE registers and
>> + * AE core bases follow
>> + */
>> + if (mcode->is_ae) {
>> + core = CPT_MAX_SE_CORES; /* start couting from 10 */
>> + total_cores = CPT_MAX_TOTAL_CORES; /* upto 15 */
>> + } else {
>> + core = 0; /* start couting from 0 */
>> + total_cores = CPT_MAX_SE_CORES; /* upto 9 */
>> + }
>> +
>> + /* Point to microcode for each core of the group */
>> + for (; core < total_cores ; core++, shift++) {
>> + if (mcode->core_mask & (1 << shift)) {
>> + cpt_write_csr64(cpt->reg_base,
>> + CPTX_PF_ENGX_UCODE_BASE(0, core),
>> + (u64)mcode->phys_base);
>> + }
>> + }
>> + return ret;
>> +}
>> +
>> +static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode)
>> +{
>> + int ret = 0;
>> + struct device *dev = &cpt->pdev->dev;
>> +
>> + /* Make device not ready */
>> + cpt->flags &= ~CPT_FLAG_DEVICE_READY;
>> + /* Disable All PF interrupts */
>> + cpt_disable_all_interrupts(cpt);
>> + /* Calculate mcode group and coremasks */
>> + if (mcode->is_ae) {
>> + if (mcode->num_cores > cpt->max_ae_cores) {
>> + dev_err(dev, "Requested for more cores than available AE cores\n");
>> + ret = -1;
>
> This is not a standard error code
>
>> + goto cpt_init_fail;
>> + }
>> +
>> + if (cpt->next_group >= CPT_MAX_CORE_GROUPS) {
>> + dev_err(dev, "Can't load, all eight microcode groups in use");
>> + return -ENFILE;
>> + }
>> +
>> + mcode->group = cpt->next_group;
>> + /* Convert requested cores to mask */
>> + mcode->core_mask = GENMASK(mcode->num_cores, 0);
>> + cpt_disable_cores(cpt, mcode->core_mask, AE_TYPES,
>> + mcode->group);
>> + /* Load microcode for AE engines */
>> + if (cpt_load_microcode(cpt, mcode)) {
>> + dev_err(dev, "Microcode load Failed for %s\n",
>> + mcode->version);
>> + ret = -1;
>
> again and you loose the error code given by cpt_load_microcode
okay
>
>> + goto cpt_init_fail;
>> + }
>> + cpt->next_group++;
>> + /* Configure group mask for the mcode */
>> + cpt_configure_group(cpt, mcode->group, mcode->core_mask,
>> + AE_TYPES);
>> + /* Enable AE cores for the group mask */
>> + cpt_enable_cores(cpt, mcode->core_mask, AE_TYPES);
>> + } else {
>> + if (mcode->num_cores > cpt->max_se_cores) {
>> + dev_err(dev, "Requested for more cores than available SE cores\n");
>> + ret = -1;
>
> Again
>
>> + goto cpt_init_fail;
>> + }
>> + if (cpt->next_group >= CPT_MAX_CORE_GROUPS) {
>> + dev_err(dev, "Can't load, all eight microcode groups in use");
>> + return -ENFILE;
>> + }
>> +
>> + mcode->group = cpt->next_group;
>> + /* Covert requested cores to mask */
>> + mcode->core_mask = GENMASK(mcode->num_cores, 0);
>> + cpt_disable_cores(cpt, mcode->core_mask, SE_TYPES,
>> + mcode->group);
>> + /* Load microcode for SE engines */
>> + if (cpt_load_microcode(cpt, mcode)) {
>> + dev_err(dev, "Microcode load Failed for %s\n",
>> + mcode->version);
>> + ret = -1;
>
> Again
>
>> + goto cpt_init_fail;
>> + }
>> + cpt->next_group++;
>> + /* Configure group mask for the mcode */
>> + cpt_configure_group(cpt, mcode->group, mcode->core_mask,
>> + SE_TYPES);
>> + /* Enable SE cores for the group mask */
>> + cpt_enable_cores(cpt, mcode->core_mask, SE_TYPES);
>> + }
>> +
>> + /* Enabled PF mailbox interrupts */
>> + cpt_enable_mbox_interrupts(cpt);
>> + cpt->flags |= CPT_FLAG_DEVICE_READY;
>> +
>> + return ret;
>> +
>> +cpt_init_fail:
>> + /* Enabled PF mailbox interrupts */
>> + cpt_enable_mbox_interrupts(cpt);
>> +
>> + return ret;
>> +}
>> +
>> +struct ucode_header {
>> + u8 version[32];
>> + u32 code_length;
>> + u32 data_length;
>> + u64 sram_address;
>> +};
>> +
>> +static int cpt_ucode_load_fw(struct cpt_device *cpt, const u8 *fw, bool is_ae)
>> +{
>> + const struct firmware *fw_entry;
>> + struct device *dev = &cpt->pdev->dev;
>> + struct ucode_header *ucode;
>> + struct microcode *mcode;
>> + int j, ret = 0;
>> +
>> + ret = request_firmware(&fw_entry, fw, dev);
>> + if (ret)
>> + return ret;
>
> I think you could also check for a minimal firmware size
Yes will add the check.
>
> [...]
>> +static void cpt_disable_all_cores(struct cpt_device *cpt)
>> +{
>> + u32 grp, timeout = 0xFFFFFFFF;
>> + struct device *dev = &cpt->pdev->dev;
>> +
>> + /* Disengage the cores from groups */
>> + for (grp = 0; grp < CPT_MAX_CORE_GROUPS; grp++) {
>> + cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 0);
>> + udelay(CSR_DELAY);
>> + }
>> +
>> + grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0));
>> + while (grp) {
>> + dev_err(dev, "Cores still busy");
>> + grp = cpt_read_csr64(cpt->reg_base,
>> + CPTX_PF_EXEC_BUSY(0));
>> + if (timeout--)
>> + break;
>> + }
>
> Same problem than cpt_disable_cores
Will adjust the timeout.
>
>> + /* Disable the cores */
>> + cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), 0);
>> +}
>> +
>> +/**
>> + * Ensure all cores are disenganed from all groups by
>
> typo engaged
>
>> + * calling cpt_disable_all_cores() before calling this
>> + * function.
>> + */
>> +static void cpt_unload_microcode(struct cpt_device *cpt)
>> +{
>> + u32 grp = 0, core;
>> +
>> + /* Free microcode bases and reset group masks */
>> + for (grp = 0; grp < CPT_MAX_CORE_GROUPS; grp++) {
>> + struct microcode *mcode = &cpt->mcode[grp];
>> +
>> + if (cpt->mcode[grp].code)
>> + dma_free_coherent(&cpt->pdev->dev, mcode->code_size,
>> + mcode->code, mcode->phys_base);
>> + mcode->code = NULL;
>> + //mcode->base = NULL;
>
> This is not a standard comment
Will get this removed.
>
>> + }
>> + /* Clear UCODE_BASE registers for all engines */
>> + for (core = 0; core < CPT_MAX_TOTAL_CORES; core++)
>> + cpt_write_csr64(cpt->reg_base,
>> + CPTX_PF_ENGX_UCODE_BASE(0, core), 0ull);
>> +}
>> +
>> +static int cpt_device_init(struct cpt_device *cpt)
>> +{
>> + u64 bist;
>> + struct device *dev = &cpt->pdev->dev;
>> +
>> + /* Reset the PF when probed first */
>> + cpt_reset(cpt);
>> + mdelay((100));
>
> double parenthesis
okay
>
>> +
>> + /*Check BIST status*/
>> + bist = (u64)cpt_check_bist_status(cpt);
>> + if (bist) {
>> + dev_err(dev, "RAM BIST failed with code 0x%llx", bist);
>> + return -ENODEV;
>> + }
>> +
>> + bist = cpt_check_exe_bist_status(cpt);
>> + if (bist) {
>> + dev_err(dev, "Engine BIST failed with code 0x%llx", bist);
>> + return -ENODEV;
>> + }
>> +
>> + /*Get CLK frequency*/
>> + /*Get max enabled cores */
>> + cpt_find_max_enabled_cores(cpt);
>> + /*Disable all cores*/
>> + cpt_disable_all_cores(cpt);
>> + /*Reset device parameters*/
>> + cpt->next_mc_idx = 0;
>> + cpt->next_group = 0;
>> + /* PF is ready */
>> + cpt->flags |= CPT_FLAG_DEVICE_READY;
>> +
>> + return 0;
>> +}
>> +
>> +static int cpt_register_interrupts(struct cpt_device *cpt)
>> +{
>> + int ret;
>> + struct device *dev = &cpt->pdev->dev;
>> +
>> + /* Enable MSI-X */
>> + ret = cpt_enable_msix(cpt);
>> + if (ret)
>> + return ret;
>> +
>> + /* Register mailbox interrupt handlers */
>> + ret = request_irq(cpt->msix_entries[CPT_PF_INT_VEC_E_MBOXX(0)].vector,
>> + cpt_mbx0_intr_handler, 0, "CPT Mbox0", cpt);
>> + if (ret)
>> + goto fail;
>> +
>> + cpt->irq_allocated[CPT_PF_INT_VEC_E_MBOXX(0)] = true;
>> +
>> + /* Enable mailbox interrupt */
>> + cpt_enable_mbox_interrupts(cpt);
>> + return 0;
>> +
>> +fail:
>> + dev_err(dev, "Request irq failed\n");
>> + cpt_free_all_interrupts(cpt);
>> + return ret;
>> +}
>> +
>> +static void cpt_unregister_interrupts(struct cpt_device *cpt)
>> +{
>> + cpt_free_all_interrupts(cpt);
>> + cpt_disable_msix(cpt);
>> +}
>> +
>> +static int cpt_sriov_init(struct cpt_device *cpt, int num_vfs)
>> +{
>> + int pos = 0;
>> + int err;
>> + u16 total_vf_cnt;
>> + struct pci_dev *pdev = cpt->pdev;
>> +
>> + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
>> + if (!pos) {
>> + dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
>> + return -ENODEV;
>> + }
>> +
>> + cpt->num_vf_en = num_vfs; /* User requested VFs */
>> + pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
>> + if (total_vf_cnt < cpt->num_vf_en)
>> + cpt->num_vf_en = total_vf_cnt;
>> +
>> + if (!total_vf_cnt)
>> + return 0;
>> +
>> + /*Enabled the available VFs */
>> + err = pci_enable_sriov(pdev, cpt->num_vf_en);
>> + if (err) {
>> + dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
>> + cpt->num_vf_en);
>> + cpt->num_vf_en = 0;
>> + return err;
>> + }
>> +
>> + /* TODO: Optionally enable static VQ priorities feature */
>> +
>> + dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
>> + cpt->num_vf_en);
>> +
>> + cpt->flags |= CPT_FLAG_SRIOV_ENABLED;
>> +
>> + return 0;
>> +}
>> +
>> +static int cpt_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct cpt_device *cpt;
>> + int err;
>> +
>> + if (num_vfs > 16) {
>> + pr_warn("Invalid vf count %d, Resetting it to 4(default)\n",
>> + num_vfs);
>
> Why not using dev_warn ?
>
>> + num_vfs = 4;
>> + }
>> +
>> + cpt = devm_kzalloc(dev, sizeof(struct cpt_device), GFP_KERNEL);
>
> Use sizeof(*cpt) like checkpatch will said.
>
> [...]
>> +static void cpt_shutdown(struct pci_dev *pdev)
>> +{
>> + struct cpt_device *cpt = pci_get_drvdata(pdev);
>> +
>> + if (!cpt)
>> + return;
>> +
>> + dev_info(&pdev->dev, "Shutdown device %x:%x.\n",
>> + (u32)pdev->vendor, (u32)pdev->device);
>> +
>> + cpt_unregister_interrupts(cpt);
>> + pci_release_regions(pdev);
>> + pci_disable_device(pdev);
>> + pci_set_drvdata(pdev, NULL);
>> + kzfree(cpt);
>
> since cpt is allocated with devm_, this kzfree is unnecessary
Noted!!
>
> Thanks
> Regards
> Corentin Labbe
>
^ permalink raw reply
* Re: [PATCH v3 2/3] drivers: crypto: Add the Virtual Function driver for CPT
From: George Cherian @ 2017-01-06 7:03 UTC (permalink / raw)
To: Corentin Labbe, george.cherian
Cc: herbert, davem, linux-kernel, linux-crypto, david.daney
In-Reply-To: <20161221140155.GB21051@Red>
Hi Corentin,
On 12/21/2016 07:31 PM, Corentin Labbe wrote:
> Hello
>
> I have some comment inline
>
> On Wed, Dec 21, 2016 at 11:56:12AM +0000, george.cherian@cavium.com wrote:
>> From: George Cherian <george.cherian@cavium.com>
>>
>> Enable the CPT VF driver. CPT is the cryptographic Accelaration Unit
>
> typo acceleration
will fix
>
> [...]
>> +static inline void update_input_data(struct cpt_request_info *req_info,
>> + struct scatterlist *inp_sg,
>> + u32 nbytes, u32 *argcnt)
>> +{
>> + req_info->req.dlen += nbytes;
>> +
>> + while (nbytes) {
>> + u32 len = min(nbytes, inp_sg->length);
>> + u8 *ptr = page_address(sg_page(inp_sg)) + inp_sg->offset;
>
> You could use sg_virt instead.
Thanks for pointing it out, Yes will replace with sg_virt.
>
> But do you have tested your accelerator with user space data (via cryptodev/AF_ALG) ?
No I have tested only using in kernel applications, Not used
cryptodev/AF_ALG
> In my memory, you better use kmap() instead of this direct memory address.
>
> [...]
>> +static inline u32 cvm_enc_dec(struct ablkcipher_request *req, u32 enc,
>> + u32 cipher_type)
>> +{
>> + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
>> + struct cvm_enc_ctx *ctx = crypto_ablkcipher_ctx(tfm);
>> + u32 key_type = AES_128_BIT;
>> + struct cvm_req_ctx *rctx = ablkcipher_request_ctx(req);
>> + u32 enc_iv_len = crypto_ablkcipher_ivsize(tfm);
>> + struct fc_context *fctx = &rctx->fctx;
>> + struct cpt_request_info *req_info = &rctx->cpt_req;
>> + void *cdev = NULL;
>> + u32 status = -1;
>
> Doable but dangerous
> Furthermore, cptvf_do_request return int so why use u32 ?
will fix it.
>
> [...]
>> +void cvm_enc_dec_exit(struct crypto_tfm *tfm)
>> +{
>> + return;
>> +}
>
> So you could remove all reference to this function
>
okay
> [...]
>> +static inline int cav_register_algs(void)
>> +{
>> + int err = 0;
>> +
>> + err = crypto_register_algs(algs, ARRAY_SIZE(algs));
>> + if (err) {
>> + pr_err("Error in aes module init %d\n", err);
>> + return -1;
>
> This is not a standard error code
>
okay
> [...]
>> diff --git a/drivers/crypto/cavium/cpt/cptvf_algs.h b/drivers/crypto/cavium/cpt/cptvf_algs.h
>> new file mode 100644
>> index 0000000..fcb287b
>> --- /dev/null
>> +++ b/drivers/crypto/cavium/cpt/cptvf_algs.h
> [...]
>> +
>> +u32 cptvf_do_request(void *cptvf, struct cpt_request_info *req);
>
> latter this function is set "return int"
>
> [...]
>> +static int cptvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct cpt_vf *cptvf;
>> + int err;
>> +
>> + cptvf = devm_kzalloc(dev, sizeof(struct cpt_vf), GFP_KERNEL);
>
> use sizeof(*cptvf) and checkpatch
>
okay
> [...]
>> +static int setup_sgio_components(struct cpt_vf *cptvf, struct buf_ptr *list,
>> + int buf_count, u8 *buffer)
>> +{
>> + int ret = 0, i, j;
>> + int components;
>> + struct sglist_component *sg_ptr = NULL;
>> + struct pci_dev *pdev = cptvf->pdev;
>> +
>> + if (unlikely(!list)) {
>> + pr_err("Input List pointer is NULL\n");
>> + ret = -EFAULT;
>> + return ret;
>
> You could directly return -EFAULT and use dev_err()
>
okay
>> + }
>> +
>> + for (i = 0; i < buf_count; i++) {
>> + if (likely(list[i].vptr)) {
>> + list[i].dma_addr = dma_map_single(&pdev->dev,
>> + list[i].vptr,
>> + list[i].size,
>> + DMA_BIDIRECTIONAL);
>> + if (unlikely(dma_mapping_error(&pdev->dev,
>> + list[i].dma_addr))) {
>> + pr_err("DMA map kernel buffer failed for component: %d\n",
>> + i);
>
> Use dev_err
>
> [...]
>> + u16 g_sz_bytes = 0, s_sz_bytes = 0;
>> + int ret = 0;
>> + struct pci_dev *pdev = cptvf->pdev;
>> +
>> + if (req->incnt > MAX_SG_IN_CNT || req->outcnt > MAX_SG_OUT_CNT) {
>> + pr_err("Requestes SG components are higher than supported\n");
>
> typo request and use dev_err
>
> In all files you have some pr_x that could be better use as dev_x
okay
>
>> + ret = -EINVAL;
>> + goto scatter_gather_clean;
>> + }
>> +
>> + /* Setup gather (input) components */
>> + g_sz_bytes = ((req->incnt + 3) / 4) * sizeof(struct sglist_component);
>> + info->gather_components = kzalloc((g_sz_bytes), GFP_KERNEL);
>
> unnecessary parenthesis
>
>> + if (!info->gather_components) {
>> + ret = -ENOMEM;
>> + goto scatter_gather_clean;
>> + }
>> +
>> + ret = setup_sgio_components(cptvf, req->in,
>> + req->incnt,
>> + info->gather_components);
>> + if (ret) {
>> + pr_err("Failed to setup gather list\n");
>> + ret = -EFAULT;
>> + goto scatter_gather_clean;
>> + }
>> +
>> + /* Setup scatter (output) components */
>> + s_sz_bytes = ((req->outcnt + 3) / 4) * sizeof(struct sglist_component);
>> + info->scatter_components = kzalloc((s_sz_bytes), GFP_KERNEL);
>
> again
>
>> + if (!info->scatter_components) {
>> + ret = -ENOMEM;
>> + goto scatter_gather_clean;
>> + }
>> +
>> + ret = setup_sgio_components(cptvf, req->out,
>> + req->outcnt,
>> + info->scatter_components);
>> + if (ret) {
>> + pr_err("Failed to setup gather list\n");
>> + ret = -EFAULT;
>> + goto scatter_gather_clean;
>
> double space
okay
>
>> + }
>> +
>> + /* Create and initialize DPTR */
>> + info->dlen = g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE;
>> + info->in_buffer = kzalloc((info->dlen), GFP_KERNEL);
>
> double parenthesis
> I will stop here, you have lots of that in all your alloc
>
okay
> [...]
>> +
>> + ret = send_cpt_command(cptvf, &cptinst, queue);
>> + spin_unlock_bh(&pqueue->lock);
>> + if (unlikely(ret)) {
>> + spin_unlock_bh(&pqueue->lock);
>
> Double unlock
>
Yes will fix it.
> [...]
>> diff --git a/drivers/crypto/cavium/cpt/request_manager.h b/drivers/crypto/cavium/cpt/request_manager.h
>> new file mode 100644
>> index 0000000..df6c306
>> --- /dev/null
>> +++ b/drivers/crypto/cavium/cpt/request_manager.h
>> @@ -0,0 +1,147 @@
>> +/*
>> + * Copyright (C) 2016 Cavium, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of version 2 of the GNU General Public License
>> + * as published by the Free Software Foundation.
>> + */
>> +
>> +#ifndef __REQUEST_MANGER_H
>> +#define __REQUEST_MANGER_H
>
> typo manager
>
okay
> Thanks
> Regards
> Corentin Labbe
>
^ permalink raw reply
* [PATCH v1 0/8] crypto:chcr- Bug fixes
From: Harsh Jain @ 2017-01-06 8:31 UTC (permalink / raw)
To: hariprasad, netdev, herbert, linux-crypto; +Cc: Harsh Jain
The patch series is based on Herbert's cryptodev-2.6 tree.
It include bug fixes.
Atul Gupta (4):
crypto:chcr-Change flow IDs
crypto:chcr- Fix panic on dma_unmap_sg
crypto:chcr- Check device is allocated before use
crypto:chcr- Fix wrong typecasting
Harsh Jain (4):
crypto:chcr- Fix key length for RFC4106
crypto:chcr- Use cipher instead of Block Cipher in gcm setkey
crypto:chcr: Change cra_flags for cipher algos
crypto:chcr- Change algo priority
drivers/crypto/chelsio/chcr_algo.c | 97 ++++++++++++++-------------
drivers/crypto/chelsio/chcr_algo.h | 9 +--
drivers/crypto/chelsio/chcr_core.c | 27 ++++----
drivers/crypto/chelsio/chcr_core.h | 1 +
drivers/crypto/chelsio/chcr_crypto.h | 5 +-
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h | 8 +++
6 files changed, 80 insertions(+), 67 deletions(-)
--
1.8.2.3
^ permalink raw reply
* [PATCH v1 2/8] crypto:chcr- Fix panic on dma_unmap_sg
From: Harsh Jain @ 2017-01-06 8:31 UTC (permalink / raw)
To: hariprasad, netdev, herbert, linux-crypto; +Cc: Harsh Jain, Atul Gupta
In-Reply-To: <cover.1483599449.git.harsh@chelsio.com>
Save DMA mapped sg list addresses to request context buffer.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
---
drivers/crypto/chelsio/chcr_algo.c | 49 +++++++++++++++++++-----------------
drivers/crypto/chelsio/chcr_crypto.h | 3 +++
2 files changed, 29 insertions(+), 23 deletions(-)
diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c
index 1d7dfcf..deec7c0 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -158,7 +158,7 @@ int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
case CRYPTO_ALG_TYPE_AEAD:
ctx_req.req.aead_req = (struct aead_request *)req;
ctx_req.ctx.reqctx = aead_request_ctx(ctx_req.req.aead_req);
- dma_unmap_sg(&u_ctx->lldi.pdev->dev, ctx_req.req.aead_req->dst,
+ dma_unmap_sg(&u_ctx->lldi.pdev->dev, ctx_req.ctx.reqctx->dst,
ctx_req.ctx.reqctx->dst_nents, DMA_FROM_DEVICE);
if (ctx_req.ctx.reqctx->skb) {
kfree_skb(ctx_req.ctx.reqctx->skb);
@@ -1364,8 +1364,7 @@ static struct sk_buff *create_authenc_wr(struct aead_request *req,
struct chcr_wr *chcr_req;
struct cpl_rx_phys_dsgl *phys_cpl;
struct phys_sge_parm sg_param;
- struct scatterlist *src, *dst;
- struct scatterlist src_sg[2], dst_sg[2];
+ struct scatterlist *src;
unsigned int frags = 0, transhdr_len;
unsigned int ivsize = crypto_aead_ivsize(tfm), dst_size = 0;
unsigned int kctx_len = 0;
@@ -1385,19 +1384,21 @@ static struct sk_buff *create_authenc_wr(struct aead_request *req,
if (sg_nents_for_len(req->src, req->assoclen + req->cryptlen) < 0)
goto err;
- src = scatterwalk_ffwd(src_sg, req->src, req->assoclen);
- dst = src;
+ src = scatterwalk_ffwd(reqctx->srcffwd, req->src, req->assoclen);
+ reqctx->dst = src;
+
if (req->src != req->dst) {
err = chcr_copy_assoc(req, aeadctx);
if (err)
return ERR_PTR(err);
- dst = scatterwalk_ffwd(dst_sg, req->dst, req->assoclen);
+ reqctx->dst = scatterwalk_ffwd(reqctx->dstffwd, req->dst,
+ req->assoclen);
}
if (get_aead_subtype(tfm) == CRYPTO_ALG_SUB_TYPE_AEAD_NULL) {
null = 1;
assoclen = 0;
}
- reqctx->dst_nents = sg_nents_for_len(dst, req->cryptlen +
+ reqctx->dst_nents = sg_nents_for_len(reqctx->dst, req->cryptlen +
(op_type ? -authsize : authsize));
if (reqctx->dst_nents <= 0) {
pr_err("AUTHENC:Invalid Destination sg entries\n");
@@ -1462,7 +1463,7 @@ static struct sk_buff *create_authenc_wr(struct aead_request *req,
sg_param.obsize = req->cryptlen + (op_type ? -authsize : authsize);
sg_param.qid = qid;
sg_param.align = 0;
- if (map_writesg_phys_cpl(&u_ctx->lldi.pdev->dev, phys_cpl, dst,
+ if (map_writesg_phys_cpl(&u_ctx->lldi.pdev->dev, phys_cpl, reqctx->dst,
&sg_param))
goto dstmap_fail;
@@ -1713,8 +1714,7 @@ static struct sk_buff *create_aead_ccm_wr(struct aead_request *req,
struct chcr_wr *chcr_req;
struct cpl_rx_phys_dsgl *phys_cpl;
struct phys_sge_parm sg_param;
- struct scatterlist *src, *dst;
- struct scatterlist src_sg[2], dst_sg[2];
+ struct scatterlist *src;
unsigned int frags = 0, transhdr_len, ivsize = AES_BLOCK_SIZE;
unsigned int dst_size = 0, kctx_len;
unsigned int sub_type;
@@ -1730,17 +1730,19 @@ static struct sk_buff *create_aead_ccm_wr(struct aead_request *req,
if (sg_nents_for_len(req->src, req->assoclen + req->cryptlen) < 0)
goto err;
sub_type = get_aead_subtype(tfm);
- src = scatterwalk_ffwd(src_sg, req->src, req->assoclen);
- dst = src;
+ src = scatterwalk_ffwd(reqctx->srcffwd, req->src, req->assoclen);
+ reqctx->dst = src;
+
if (req->src != req->dst) {
err = chcr_copy_assoc(req, aeadctx);
if (err) {
pr_err("AAD copy to destination buffer fails\n");
return ERR_PTR(err);
}
- dst = scatterwalk_ffwd(dst_sg, req->dst, req->assoclen);
+ reqctx->dst = scatterwalk_ffwd(reqctx->dstffwd, req->dst,
+ req->assoclen);
}
- reqctx->dst_nents = sg_nents_for_len(dst, req->cryptlen +
+ reqctx->dst_nents = sg_nents_for_len(reqctx->dst, req->cryptlen +
(op_type ? -authsize : authsize));
if (reqctx->dst_nents <= 0) {
pr_err("CCM:Invalid Destination sg entries\n");
@@ -1779,7 +1781,7 @@ static struct sk_buff *create_aead_ccm_wr(struct aead_request *req,
sg_param.obsize = req->cryptlen + (op_type ? -authsize : authsize);
sg_param.qid = qid;
sg_param.align = 0;
- if (map_writesg_phys_cpl(&u_ctx->lldi.pdev->dev, phys_cpl, dst,
+ if (map_writesg_phys_cpl(&u_ctx->lldi.pdev->dev, phys_cpl, reqctx->dst,
&sg_param))
goto dstmap_fail;
@@ -1811,8 +1813,7 @@ static struct sk_buff *create_gcm_wr(struct aead_request *req,
struct chcr_wr *chcr_req;
struct cpl_rx_phys_dsgl *phys_cpl;
struct phys_sge_parm sg_param;
- struct scatterlist *src, *dst;
- struct scatterlist src_sg[2], dst_sg[2];
+ struct scatterlist *src;
unsigned int frags = 0, transhdr_len;
unsigned int ivsize = AES_BLOCK_SIZE;
unsigned int dst_size = 0, kctx_len;
@@ -1834,13 +1835,14 @@ static struct sk_buff *create_gcm_wr(struct aead_request *req,
if (sg_nents_for_len(req->src, req->assoclen + req->cryptlen) < 0)
goto err;
- src = scatterwalk_ffwd(src_sg, req->src, req->assoclen);
- dst = src;
+ src = scatterwalk_ffwd(reqctx->srcffwd, req->src, req->assoclen);
+ reqctx->dst = src;
if (req->src != req->dst) {
err = chcr_copy_assoc(req, aeadctx);
if (err)
return ERR_PTR(err);
- dst = scatterwalk_ffwd(dst_sg, req->dst, req->assoclen);
+ reqctx->dst = scatterwalk_ffwd(reqctx->dstffwd, req->dst,
+ req->assoclen);
}
if (!req->cryptlen)
@@ -1850,7 +1852,7 @@ static struct sk_buff *create_gcm_wr(struct aead_request *req,
crypt_len = AES_BLOCK_SIZE;
else
crypt_len = req->cryptlen;
- reqctx->dst_nents = sg_nents_for_len(dst, req->cryptlen +
+ reqctx->dst_nents = sg_nents_for_len(reqctx->dst, req->cryptlen +
(op_type ? -authsize : authsize));
if (reqctx->dst_nents <= 0) {
pr_err("GCM:Invalid Destination sg entries\n");
@@ -1925,7 +1927,7 @@ static struct sk_buff *create_gcm_wr(struct aead_request *req,
sg_param.obsize = req->cryptlen + (op_type ? -authsize : authsize);
sg_param.qid = qid;
sg_param.align = 0;
- if (map_writesg_phys_cpl(&u_ctx->lldi.pdev->dev, phys_cpl, dst,
+ if (map_writesg_phys_cpl(&u_ctx->lldi.pdev->dev, phys_cpl, reqctx->dst,
&sg_param))
goto dstmap_fail;
@@ -1939,7 +1941,8 @@ static struct sk_buff *create_gcm_wr(struct aead_request *req,
write_sg_to_skb(skb, &frags, src, req->cryptlen);
} else {
aes_gcm_empty_pld_pad(req->dst, authsize - 1);
- write_sg_to_skb(skb, &frags, dst, crypt_len);
+ write_sg_to_skb(skb, &frags, reqctx->dst, crypt_len);
+
}
create_wreq(ctx, chcr_req, req, skb, kctx_len, size, 1,
diff --git a/drivers/crypto/chelsio/chcr_crypto.h b/drivers/crypto/chelsio/chcr_crypto.h
index d5af7d6..7ec0a8f 100644
--- a/drivers/crypto/chelsio/chcr_crypto.h
+++ b/drivers/crypto/chelsio/chcr_crypto.h
@@ -158,6 +158,9 @@ struct ablk_ctx {
};
struct chcr_aead_reqctx {
struct sk_buff *skb;
+ struct scatterlist *dst;
+ struct scatterlist srcffwd[2];
+ struct scatterlist dstffwd[2];
short int dst_nents;
u16 verify;
u8 iv[CHCR_MAX_CRYPTO_IV_LEN];
--
1.8.2.3
^ permalink raw reply related
* [PATCH v1 3/8] crypto:chcr- Fix key length for RFC4106
From: Harsh Jain @ 2017-01-06 8:31 UTC (permalink / raw)
To: hariprasad, netdev, herbert, linux-crypto; +Cc: Harsh Jain
In-Reply-To: <cover.1483599449.git.harsh@chelsio.com>
Check keylen before copying salt to avoid wrap around of Integer.
Signed-off-by: Harsh Jain <harsh@chelsio.com>
---
drivers/crypto/chelsio/chcr_algo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c
index deec7c0..6c2dea3 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -2194,8 +2194,8 @@ static int chcr_gcm_setkey(struct crypto_aead *aead, const u8 *key,
unsigned int ck_size;
int ret = 0, key_ctx_size = 0;
- if (get_aead_subtype(aead) ==
- CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106) {
+ if (get_aead_subtype(aead) == CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106 &&
+ keylen > 3) {
keylen -= 4; /* nonce/salt is present in the last 4 bytes */
memcpy(aeadctx->salt, key + keylen, 4);
}
--
1.8.2.3
^ permalink raw reply related
* [PATCH v1 4/8] crypto:chcr- Use cipher instead of Block Cipher in gcm setkey
From: Harsh Jain @ 2017-01-06 8:31 UTC (permalink / raw)
To: hariprasad, netdev, herbert, linux-crypto; +Cc: Harsh Jain
In-Reply-To: <cover.1483599449.git.harsh@chelsio.com>
1 Block of encrption can be done with aes-generic. no need of
cbc(aes). This patch replaces cbc(aes-generic) with aes-generic.
Signed-off-by: Harsh Jain <harsh@chelsio.com>
---
drivers/crypto/chelsio/chcr_algo.c | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c
index 6c2dea3..d335943 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -2189,8 +2189,7 @@ static int chcr_gcm_setkey(struct crypto_aead *aead, const u8 *key,
struct chcr_context *ctx = crypto_aead_ctx(aead);
struct chcr_aead_ctx *aeadctx = AEAD_CTX(ctx);
struct chcr_gcm_ctx *gctx = GCM_CTX(aeadctx);
- struct blkcipher_desc h_desc;
- struct scatterlist src[1];
+ struct crypto_cipher *cipher;
unsigned int ck_size;
int ret = 0, key_ctx_size = 0;
@@ -2223,27 +2222,26 @@ static int chcr_gcm_setkey(struct crypto_aead *aead, const u8 *key,
CHCR_KEYCTX_MAC_KEY_SIZE_128,
0, 0,
key_ctx_size >> 4);
- /* Calculate the H = CIPH(K, 0 repeated 16 times) using sync aes
- * blkcipher It will go on key context
+ /* Calculate the H = CIPH(K, 0 repeated 16 times).
+ * It will go in key context
*/
- h_desc.tfm = crypto_alloc_blkcipher("cbc(aes-generic)", 0, 0);
- if (IS_ERR(h_desc.tfm)) {
+ cipher = crypto_alloc_cipher("aes-generic", 0, 0);
+ if (IS_ERR(cipher)) {
aeadctx->enckey_len = 0;
ret = -ENOMEM;
goto out;
}
- h_desc.flags = 0;
- ret = crypto_blkcipher_setkey(h_desc.tfm, key, keylen);
+
+ ret = crypto_cipher_setkey(cipher, key, keylen);
if (ret) {
aeadctx->enckey_len = 0;
goto out1;
}
memset(gctx->ghash_h, 0, AEAD_H_SIZE);
- sg_init_one(&src[0], gctx->ghash_h, AEAD_H_SIZE);
- ret = crypto_blkcipher_encrypt(&h_desc, &src[0], &src[0], AEAD_H_SIZE);
+ crypto_cipher_encrypt_one(cipher, gctx->ghash_h, gctx->ghash_h);
out1:
- crypto_free_blkcipher(h_desc.tfm);
+ crypto_free_cipher(cipher);
out:
return ret;
}
--
1.8.2.3
^ permalink raw reply related
* [PATCH v1 5/8] crypto:chcr: Change cra_flags for cipher algos
From: Harsh Jain @ 2017-01-06 8:31 UTC (permalink / raw)
To: hariprasad, netdev, herbert, linux-crypto; +Cc: Harsh Jain
In-Reply-To: <cover.1483599449.git.harsh@chelsio.com>
Change cipher algos flags to CRYPTO_ALG_TYPE_ABLKCIPHER.
Signed-off-by: Harsh Jain <harsh@chelsio.com>
---
drivers/crypto/chelsio/chcr_algo.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c
index d335943..21fc04c 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -171,7 +171,7 @@ int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
}
break;
- case CRYPTO_ALG_TYPE_BLKCIPHER:
+ case CRYPTO_ALG_TYPE_ABLKCIPHER:
ctx_req.req.ablk_req = (struct ablkcipher_request *)req;
ctx_req.ctx.ablk_ctx =
ablkcipher_request_ctx(ctx_req.req.ablk_req);
@@ -2492,7 +2492,7 @@ static int chcr_aead_op(struct aead_request *req,
.cra_name = "cbc(aes)",
.cra_driver_name = "cbc-aes-chcr",
.cra_priority = CHCR_CRA_PRIORITY,
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct chcr_context)
@@ -2519,7 +2519,7 @@ static int chcr_aead_op(struct aead_request *req,
.cra_name = "xts(aes)",
.cra_driver_name = "xts-aes-chcr",
.cra_priority = CHCR_CRA_PRIORITY,
- .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
CRYPTO_ALG_ASYNC,
.cra_blocksize = AES_BLOCK_SIZE,
.cra_ctxsize = sizeof(struct chcr_context) +
--
1.8.2.3
^ permalink raw reply related
* [PATCH v1 6/8] crypto:chcr- Change algo priority
From: Harsh Jain @ 2017-01-06 8:31 UTC (permalink / raw)
To: hariprasad, netdev, herbert, linux-crypto; +Cc: Harsh Jain
In-Reply-To: <cover.1483599449.git.harsh@chelsio.com>
Update priorities to 3000
Signed-off-by: Harsh Jain <harsh@chelsio.com>
---
drivers/crypto/chelsio/chcr_crypto.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/chelsio/chcr_crypto.h b/drivers/crypto/chelsio/chcr_crypto.h
index 7ec0a8f..81cfd0b 100644
--- a/drivers/crypto/chelsio/chcr_crypto.h
+++ b/drivers/crypto/chelsio/chcr_crypto.h
@@ -48,7 +48,7 @@
* giving the processed data
*/
-#define CHCR_CRA_PRIORITY 300
+#define CHCR_CRA_PRIORITY 3000
#define CHCR_AES_MAX_KEY_LEN (2 * (AES_MAX_KEY_SIZE)) /* consider xts */
#define CHCR_MAX_CRYPTO_IV_LEN 16 /* AES IV len */
--
1.8.2.3
^ permalink raw reply related
* [PATCH v1 7/8] crypto:chcr- Check device is allocated before use
From: Harsh Jain @ 2017-01-06 8:31 UTC (permalink / raw)
To: hariprasad, netdev, herbert, linux-crypto; +Cc: Harsh Jain, Atul Gupta
In-Reply-To: <cover.1483599449.git.harsh@chelsio.com>
Ensure dev is allocated for crypto uld context before using the device
for crypto operations.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
---
drivers/crypto/chelsio/chcr_core.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/crypto/chelsio/chcr_core.c b/drivers/crypto/chelsio/chcr_core.c
index 918da8e..1c65f07 100644
--- a/drivers/crypto/chelsio/chcr_core.c
+++ b/drivers/crypto/chelsio/chcr_core.c
@@ -52,6 +52,7 @@
int assign_chcr_device(struct chcr_dev **dev)
{
struct uld_ctx *u_ctx;
+ int ret = -ENXIO;
/*
* Which device to use if multiple devices are available TODO
@@ -59,15 +60,14 @@ int assign_chcr_device(struct chcr_dev **dev)
* must go to the same device to maintain the ordering.
*/
mutex_lock(&dev_mutex); /* TODO ? */
- u_ctx = list_first_entry(&uld_ctx_list, struct uld_ctx, entry);
- if (!u_ctx) {
- mutex_unlock(&dev_mutex);
- return -ENXIO;
+ list_for_each_entry(u_ctx, &uld_ctx_list, entry)
+ if (u_ctx && u_ctx->dev) {
+ *dev = u_ctx->dev;
+ ret = 0;
+ break;
}
-
- *dev = u_ctx->dev;
mutex_unlock(&dev_mutex);
- return 0;
+ return ret;
}
static int chcr_dev_add(struct uld_ctx *u_ctx)
@@ -202,10 +202,8 @@ static int chcr_uld_state_change(void *handle, enum cxgb4_state state)
static int __init chcr_crypto_init(void)
{
- if (cxgb4_register_uld(CXGB4_ULD_CRYPTO, &chcr_uld_info)) {
+ if (cxgb4_register_uld(CXGB4_ULD_CRYPTO, &chcr_uld_info))
pr_err("ULD register fail: No chcr crypto support in cxgb4");
- return -1;
- }
return 0;
}
--
1.8.2.3
^ permalink raw reply related
* [PATCH v1 8/8] crypto:chcr- Fix wrong typecasting
From: Harsh Jain @ 2017-01-06 8:31 UTC (permalink / raw)
To: hariprasad, netdev, herbert, linux-crypto; +Cc: Harsh Jain, Atul Gupta
In-Reply-To: <cover.1483599449.git.harsh@chelsio.com>
Typecast the pointer with correct structure.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
---
drivers/crypto/chelsio/chcr_core.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/chelsio/chcr_core.c b/drivers/crypto/chelsio/chcr_core.c
index 1c65f07..aec3562 100644
--- a/drivers/crypto/chelsio/chcr_core.c
+++ b/drivers/crypto/chelsio/chcr_core.c
@@ -151,18 +151,17 @@ int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
{
struct uld_ctx *u_ctx = (struct uld_ctx *)handle;
struct chcr_dev *dev = u_ctx->dev;
- const struct cpl_act_establish *rpl = (struct cpl_act_establish
- *)rsp;
+ const struct cpl_fw6_pld *rpl = (struct cpl_fw6_pld *)rsp;
- if (rpl->ot.opcode != CPL_FW6_PLD) {
+ if (rpl->opcode != CPL_FW6_PLD) {
pr_err("Unsupported opcode\n");
return 0;
}
if (!pgl)
- work_handlers[rpl->ot.opcode](dev, (unsigned char *)&rsp[1]);
+ work_handlers[rpl->opcode](dev, (unsigned char *)&rsp[1]);
else
- work_handlers[rpl->ot.opcode](dev, pgl->va);
+ work_handlers[rpl->opcode](dev, pgl->va);
return 0;
}
--
1.8.2.3
^ permalink raw reply related
* [PATCH v1 1/8] crypto:chcr-Change flow IDs
From: Harsh Jain @ 2017-01-06 8:31 UTC (permalink / raw)
To: hariprasad, netdev, herbert, linux-crypto; +Cc: Harsh Jain, Atul Gupta
In-Reply-To: <cover.1483599449.git.harsh@chelsio.com>
Change assign flowc id to each outgoing request.Firmware use flowc id
to schedule each request onto HW.
Reviewed-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
---
drivers/crypto/chelsio/chcr_algo.c | 18 ++++++++++--------
drivers/crypto/chelsio/chcr_algo.h | 9 +++++----
drivers/crypto/chelsio/chcr_core.h | 1 +
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h | 8 ++++++++
4 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c
index 2ed1e24..1d7dfcf 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -542,10 +542,11 @@ static inline void create_wreq(struct chcr_context *ctx,
(calc_tx_flits_ofld(skb) * 8), 16)));
chcr_req->wreq.cookie = cpu_to_be64((uintptr_t)req);
chcr_req->wreq.rx_chid_to_rx_q_id =
- FILL_WR_RX_Q_ID(ctx->dev->tx_channel_id, qid,
- is_iv ? iv_loc : IV_NOP);
+ FILL_WR_RX_Q_ID(ctx->dev->rx_channel_id, qid,
+ is_iv ? iv_loc : IV_NOP, ctx->tx_channel_id);
- chcr_req->ulptx.cmd_dest = FILL_ULPTX_CMD_DEST(ctx->dev->tx_channel_id);
+ chcr_req->ulptx.cmd_dest = FILL_ULPTX_CMD_DEST(ctx->dev->tx_channel_id,
+ qid);
chcr_req->ulptx.len = htonl((DIV_ROUND_UP((calc_tx_flits_ofld(skb) * 8),
16) - ((sizeof(chcr_req->wreq)) >> 4)));
@@ -606,7 +607,7 @@ static inline void create_wreq(struct chcr_context *ctx,
chcr_req = (struct chcr_wr *)__skb_put(skb, transhdr_len);
memset(chcr_req, 0, transhdr_len);
chcr_req->sec_cpl.op_ivinsrtofst =
- FILL_SEC_CPL_OP_IVINSR(ctx->dev->tx_channel_id, 2, 1);
+ FILL_SEC_CPL_OP_IVINSR(ctx->dev->rx_channel_id, 2, 1);
chcr_req->sec_cpl.pldlen = htonl(ivsize + req->nbytes);
chcr_req->sec_cpl.aadstart_cipherstop_hi =
@@ -782,6 +783,7 @@ static int chcr_device_init(struct chcr_context *ctx)
spin_lock(&ctx->dev->lock_chcr_dev);
ctx->tx_channel_id = rxq_idx;
ctx->dev->tx_channel_id = !ctx->dev->tx_channel_id;
+ ctx->dev->rx_channel_id = 0;
spin_unlock(&ctx->dev->lock_chcr_dev);
}
out:
@@ -874,7 +876,7 @@ static struct sk_buff *create_hash_wr(struct ahash_request *req,
memset(chcr_req, 0, transhdr_len);
chcr_req->sec_cpl.op_ivinsrtofst =
- FILL_SEC_CPL_OP_IVINSR(ctx->dev->tx_channel_id, 2, 0);
+ FILL_SEC_CPL_OP_IVINSR(ctx->dev->rx_channel_id, 2, 0);
chcr_req->sec_cpl.pldlen = htonl(param->bfr_len + param->sg_len);
chcr_req->sec_cpl.aadstart_cipherstop_hi =
@@ -1424,7 +1426,7 @@ static struct sk_buff *create_authenc_wr(struct aead_request *req,
* to the hardware spec
*/
chcr_req->sec_cpl.op_ivinsrtofst =
- FILL_SEC_CPL_OP_IVINSR(ctx->dev->tx_channel_id, 2,
+ FILL_SEC_CPL_OP_IVINSR(ctx->dev->rx_channel_id, 2,
(ivsize ? (assoclen + 1) : 0));
chcr_req->sec_cpl.pldlen = htonl(assoclen + ivsize + req->cryptlen);
chcr_req->sec_cpl.aadstart_cipherstop_hi = FILL_SEC_CPL_CIPHERSTOP_HI(
@@ -1600,7 +1602,7 @@ static void fill_sec_cpl_for_aead(struct cpl_tx_sec_pdu *sec_cpl,
unsigned int ivsize = AES_BLOCK_SIZE;
unsigned int cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_CCM;
unsigned int mac_mode = CHCR_SCMD_AUTH_MODE_CBCMAC;
- unsigned int c_id = chcrctx->dev->tx_channel_id;
+ unsigned int c_id = chcrctx->dev->rx_channel_id;
unsigned int ccm_xtra;
unsigned char tag_offset = 0, auth_offset = 0;
unsigned char hmac_ctrl = get_hmac(crypto_aead_authsize(tfm));
@@ -1875,7 +1877,7 @@ static struct sk_buff *create_gcm_wr(struct aead_request *req,
tag_offset = (op_type == CHCR_ENCRYPT_OP) ? 0 : authsize;
chcr_req->sec_cpl.op_ivinsrtofst = FILL_SEC_CPL_OP_IVINSR(
- ctx->dev->tx_channel_id, 2, (ivsize ?
+ ctx->dev->rx_channel_id, 2, (ivsize ?
(req->assoclen + 1) : 0));
chcr_req->sec_cpl.pldlen = htonl(req->assoclen + ivsize + crypt_len);
chcr_req->sec_cpl.aadstart_cipherstop_hi = FILL_SEC_CPL_CIPHERSTOP_HI(
diff --git a/drivers/crypto/chelsio/chcr_algo.h b/drivers/crypto/chelsio/chcr_algo.h
index 3c7c51f..ba38bae 100644
--- a/drivers/crypto/chelsio/chcr_algo.h
+++ b/drivers/crypto/chelsio/chcr_algo.h
@@ -185,20 +185,21 @@
FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(1) | \
FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V((ctx_len)))
-#define FILL_WR_RX_Q_ID(cid, qid, wr_iv) \
+#define FILL_WR_RX_Q_ID(cid, qid, wr_iv, fid) \
htonl( \
FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V((cid)) | \
FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V((qid)) | \
FW_CRYPTO_LOOKASIDE_WR_LCB_V(0) | \
- FW_CRYPTO_LOOKASIDE_WR_IV_V((wr_iv)))
+ FW_CRYPTO_LOOKASIDE_WR_IV_V((wr_iv)) | \
+ FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(fid))
-#define FILL_ULPTX_CMD_DEST(cid) \
+#define FILL_ULPTX_CMD_DEST(cid, qid) \
htonl(ULPTX_CMD_V(ULP_TX_PKT) | \
ULP_TXPKT_DEST_V(0) | \
ULP_TXPKT_DATAMODIFY_V(0) | \
ULP_TXPKT_CHANNELID_V((cid)) | \
ULP_TXPKT_RO_V(1) | \
- ULP_TXPKT_FID_V(0))
+ ULP_TXPKT_FID_V(qid))
#define KEYCTX_ALIGN_PAD(bs) ({unsigned int _bs = (bs);\
_bs == SHA1_DIGEST_SIZE ? 12 : 0; })
diff --git a/drivers/crypto/chelsio/chcr_core.h b/drivers/crypto/chelsio/chcr_core.h
index c7088a4..79da22b 100644
--- a/drivers/crypto/chelsio/chcr_core.h
+++ b/drivers/crypto/chelsio/chcr_core.h
@@ -75,6 +75,7 @@ struct chcr_dev {
spinlock_t lock_chcr_dev;
struct uld_ctx *u_ctx;
unsigned char tx_channel_id;
+ unsigned char rx_channel_id;
};
struct uld_ctx {
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
index 8d9e4b7..ccc05f8 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
@@ -3385,6 +3385,14 @@ struct fw_crypto_lookaside_wr {
#define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
(((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
+#define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15
+#define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0xff
+#define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \
+ ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S)
+#define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \
+ (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \
+ FW_CRYPTO_LOOKASIDE_WR_FQIDX_M)
+
#define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
#define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
#define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
--
1.8.2.3
^ permalink raw reply related
* Re: Geode LX AES/RNG driver triggers warning
From: PrasannaKumar Muralidharan @ 2017-01-06 9:40 UTC (permalink / raw)
To: One Thousand Gnomes
Cc: David Gstir, linux-geode, linux-crypto, linux-kernel, teheo,
Richard Weinberger
In-Reply-To: <20170103145203.780d3c58@lxorguk.ukuu.org.uk>
>> I narrowed it down to commit 6e9b5e76882c ("hwrng: geode - Migrate to managed API") which seems to introduce this. It looks to me like some issue between devres, the Geode hwrng and AES drivers which both use the same PCI device.
>
> It does
>
>> I'm no expert here, but I curious if this will cause any issues when using the hardware crypto drivers and also what's the best way to get rid of this?
>
> Probably to create an mfd device that turns the PCI device into two MFD
> devices and bind AES and hwrng one to each MFD device. Take a look in
> drivers/mfd. That would also fix the uglies in mod_init for the rng
> driver.
I am the author of that commit. Code before commit 6e9b5e76882c had
ioremap, wondering why there was no warning message before. Just want
to know if that commit uncovered existing issue or introduced a new
issue? As far as I understand the commit did not change the
functionality. Please feel free to correct if I have missed something.
Regards,
PrasannaKumar
^ permalink raw reply
* [RFT PATCH] crypto: arm/aes - replace scalar AES cipher
From: Ard Biesheuvel @ 2017-01-06 11:53 UTC (permalink / raw)
To: linux-crypto, linux-arm-kernel; +Cc: linux, Ard Biesheuvel, herbert, nico
This replaces the scalar AES cipher that originates in the OpenSSL project
with a new implementation that is ~15% (*) faster (on modern cores), and
reuses the lookup tables and the key schedule generation routines from the
generic C implementation (which is usually compiled in anyway due to
networking and other subsystems depending on it).
Note that the bit sliced NEON code for AES still depends on the scalar cipher
that this patch replaces, so it is not removed entirely yet.
* On Cortex-A57, the performance increases from 17.0 to 14.9 cycles per byte
for 128-bit keys.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
It makes sense to test this on a variety of cores before deciding whether
to merge it or not. Test results welcome. (insmod tcrypt.ko mode=200 sec=1)
arch/arm/crypto/Kconfig | 20 +--
arch/arm/crypto/Makefile | 4 +-
arch/arm/crypto/aes-cipher-core.S | 169 ++++++++++++++++++++
arch/arm/crypto/aes-cipher-glue.c | 69 ++++++++
arch/arm/crypto/aes_glue.c | 98 ------------
5 files changed, 241 insertions(+), 119 deletions(-)
diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig
index 2f3339f015d3..f1de658c3c8f 100644
--- a/arch/arm/crypto/Kconfig
+++ b/arch/arm/crypto/Kconfig
@@ -62,33 +62,15 @@ config CRYPTO_SHA512_ARM
using optimized ARM assembler and NEON, when available.
config CRYPTO_AES_ARM
- tristate "AES cipher algorithms (ARM-asm)"
- depends on ARM
+ tristate "Scalar AES cipher for ARM"
select CRYPTO_ALGAPI
select CRYPTO_AES
help
Use optimized AES assembler routines for ARM platforms.
- AES cipher algorithms (FIPS-197). AES uses the Rijndael
- algorithm.
-
- Rijndael appears to be consistently a very good performer in
- both hardware and software across a wide range of computing
- environments regardless of its use in feedback or non-feedback
- modes. Its key setup time is excellent, and its key agility is
- good. Rijndael's very low memory requirements make it very well
- suited for restricted-space environments, in which it also
- demonstrates excellent performance. Rijndael's operations are
- among the easiest to defend against power and timing attacks.
-
- The AES specifies three key sizes: 128, 192 and 256 bits
-
- See <http://csrc.nist.gov/encryption/aes/> for more information.
-
config CRYPTO_AES_ARM_BS
tristate "Bit sliced AES using NEON instructions"
depends on KERNEL_MODE_NEON
- select CRYPTO_AES_ARM
select CRYPTO_BLKCIPHER
select CRYPTO_SIMD
help
diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile
index 8d74e55eacd4..8f5de2db701c 100644
--- a/arch/arm/crypto/Makefile
+++ b/arch/arm/crypto/Makefile
@@ -27,8 +27,8 @@ $(warning $(ce-obj-y) $(ce-obj-m))
endif
endif
-aes-arm-y := aes-armv4.o aes_glue.o
-aes-arm-bs-y := aesbs-core.o aesbs-glue.o
+aes-arm-y := aes-cipher-core.o aes-cipher-glue.o
+aes-arm-bs-y := aes-armv4.o aesbs-core.o aesbs-glue.o
sha1-arm-y := sha1-armv4-large.o sha1_glue.o
sha1-arm-neon-y := sha1-armv7-neon.o sha1_neon_glue.o
sha256-arm-neon-$(CONFIG_KERNEL_MODE_NEON) := sha256_neon_glue.o
diff --git a/arch/arm/crypto/aes-cipher-core.S b/arch/arm/crypto/aes-cipher-core.S
new file mode 100644
index 000000000000..8d4a15364d43
--- /dev/null
+++ b/arch/arm/crypto/aes-cipher-core.S
@@ -0,0 +1,169 @@
+/*
+ * Scalar AES core transform
+ *
+ * Copyright (C) 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+
+ .text
+ .align 5
+
+ rk .req r0
+ rounds .req r1
+ in .req r2
+ out .req r3
+ tt .req ip
+
+ t0 .req lr
+ t1 .req r2
+ t2 .req r3
+
+ .macro __select, out, in, idx
+ .if __LINUX_ARM_ARCH__ < 7
+ and \out, \in, #0xff << (8 * \idx)
+ .else
+ ubfx \out, \in, #(8 * \idx), #8
+ .endif
+ .endm
+
+ .macro __load, out, in, idx
+ .if __LINUX_ARM_ARCH__ < 7 && \idx > 0
+ ldr \out, [tt, \in, lsr #(8 * \idx) - 2]
+ .else
+ ldr \out, [tt, \in, lsl #2]
+ .endif
+ .endm
+
+ .macro __hround, out0, out1, in0, in1, in2, in3, t3, t4, enc
+ __select \out0, \in0, 0
+ __select t0, \in1, 1
+ __load \out0, \out0, 0
+ __load t0, t0, 1
+
+ .if \enc
+ __select \out1, \in1, 0
+ __select t1, \in2, 1
+ .else
+ __select \out1, \in3, 0
+ __select t1, \in0, 1
+ .endif
+ __load \out1, \out1, 0
+ __select t2, \in2, 2
+ __load t1, t1, 1
+ __load t2, t2, 2
+
+ eor \out0, \out0, t0, ror #24
+
+ __select t0, \in3, 3
+ .if \enc
+ __select \t3, \in3, 2
+ __select \t4, \in0, 3
+ .else
+ __select \t3, \in1, 2
+ __select \t4, \in2, 3
+ .endif
+ __load \t3, \t3, 2
+ __load t0, t0, 3
+ __load \t4, \t4, 3
+
+ eor \out1, \out1, t1, ror #24
+ eor \out0, \out0, t2, ror #16
+ ldm rk!, {t1, t2}
+ eor \out1, \out1, \t3, ror #16
+ eor \out0, \out0, t0, ror #8
+ eor \out1, \out1, \t4, ror #8
+ eor \out0, \out0, t1
+ eor \out1, \out1, t2
+ .endm
+
+ .macro fround, out0, out1, out2, out3, in0, in1, in2, in3
+ __hround \out0, \out1, \in0, \in1, \in2, \in3, \out2, \out3, 1
+ __hround \out2, \out3, \in2, \in3, \in0, \in1, \in1, \in2, 1
+ .endm
+
+ .macro iround, out0, out1, out2, out3, in0, in1, in2, in3
+ __hround \out0, \out1, \in0, \in3, \in2, \in1, \out2, \out3, 0
+ __hround \out2, \out3, \in2, \in1, \in0, \in3, \in1, \in0, 0
+ .endm
+
+ .macro __rev, out, in
+ .if __LINUX_ARM_ARCH__ < 7
+ lsl t0, \in, #24
+ and t1, \in, #0xff00
+ and t2, \in, #0xff0000
+ orr \out, t0, \in, lsr #24
+ orr \out, \out, t1, lsl #8
+ orr \out, \out, t2, lsr #8
+ .else
+ rev \out, \in
+ .endif
+ .endm
+
+ .macro do_crypt, round, ttab, ltab
+ push {r3-r11, lr}
+
+ ldr r4, [in]
+ ldr r5, [in, #4]
+ ldr r6, [in, #8]
+ ldr r7, [in, #12]
+
+ ldm rk!, {r8, r9, r10, r11}
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ __rev r4, r4
+ __rev r5, r5
+ __rev r6, r6
+ __rev r7, r7
+#endif
+
+ eor r4, r4, r8
+ eor r5, r5, r9
+ eor r6, r6, r10
+ eor r7, r7, r11
+
+ ldr tt, =\ttab
+
+ tst rounds, #2
+ bne 1f
+
+0: \round r8, r9, r10, r11, r4, r5, r6, r7
+ \round r4, r5, r6, r7, r8, r9, r10, r11
+
+1: subs rounds, rounds, #4
+ \round r8, r9, r10, r11, r4, r5, r6, r7
+ ldrls tt, =\ltab
+ \round r4, r5, r6, r7, r8, r9, r10, r11
+ bhi 0b
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ __rev r4, r4
+ __rev r5, r5
+ __rev r6, r6
+ __rev r7, r7
+#endif
+
+ ldr out, [sp]
+
+ str r4, [out]
+ str r5, [out, #4]
+ str r6, [out, #8]
+ str r7, [out, #12]
+
+ pop {r3-r11, pc}
+
+ .align 3
+ .ltorg
+ .endm
+
+ENTRY(__aes_arm_encrypt)
+ do_crypt fround, crypto_ft_tab, crypto_fl_tab
+ENDPROC(__aes_arm_encrypt)
+
+ENTRY(__aes_arm_decrypt)
+ do_crypt iround, crypto_it_tab, crypto_il_tab
+ENDPROC(__aes_arm_decrypt)
diff --git a/arch/arm/crypto/aes-cipher-glue.c b/arch/arm/crypto/aes-cipher-glue.c
new file mode 100644
index 000000000000..19545237112a
--- /dev/null
+++ b/arch/arm/crypto/aes-cipher-glue.c
@@ -0,0 +1,69 @@
+/*
+ * Scalar AES core transform
+ *
+ * Copyright (C) 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <crypto/aes.h>
+#include <linux/crypto.h>
+#include <linux/module.h>
+
+asmlinkage void __aes_arm_encrypt(u32 *rk, int rounds, const u8 *in, u8 *out);
+EXPORT_SYMBOL(__aes_arm_encrypt);
+
+asmlinkage void __aes_arm_decrypt(u32 *rk, int rounds, const u8 *in, u8 *out);
+EXPORT_SYMBOL(__aes_arm_decrypt);
+
+static void aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+ struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+ int rounds = 6 + ctx->key_length / 4;
+
+ __aes_arm_encrypt(ctx->key_enc, rounds, in, out);
+}
+
+static void aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
+{
+ struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
+ int rounds = 6 + ctx->key_length / 4;
+
+ __aes_arm_decrypt(ctx->key_dec, rounds, in, out);
+}
+
+static struct crypto_alg aes_alg = {
+ .cra_name = "aes",
+ .cra_driver_name = "aes-arm",
+ .cra_priority = 200,
+ .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_ctxsize = sizeof(struct crypto_aes_ctx),
+ .cra_module = THIS_MODULE,
+
+ .cra_cipher.cia_min_keysize = AES_MIN_KEY_SIZE,
+ .cra_cipher.cia_max_keysize = AES_MAX_KEY_SIZE,
+ .cra_cipher.cia_setkey = crypto_aes_set_key,
+ .cra_cipher.cia_encrypt = aes_encrypt,
+ .cra_cipher.cia_decrypt = aes_decrypt
+};
+
+static int __init aes_init(void)
+{
+ return crypto_register_alg(&aes_alg);
+}
+
+static void __exit aes_fini(void)
+{
+ crypto_unregister_alg(&aes_alg);
+}
+
+module_init(aes_init);
+module_exit(aes_fini);
+
+MODULE_DESCRIPTION("Scalar AES cipher for ARM");
+MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS_CRYPTO("aes");
diff --git a/arch/arm/crypto/aes_glue.c b/arch/arm/crypto/aes_glue.c
deleted file mode 100644
index 0409b8f89782..000000000000
--- a/arch/arm/crypto/aes_glue.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Glue Code for the asm optimized version of the AES Cipher Algorithm
- */
-
-#include <linux/module.h>
-#include <linux/crypto.h>
-#include <crypto/aes.h>
-
-#include "aes_glue.h"
-
-EXPORT_SYMBOL(AES_encrypt);
-EXPORT_SYMBOL(AES_decrypt);
-EXPORT_SYMBOL(private_AES_set_encrypt_key);
-EXPORT_SYMBOL(private_AES_set_decrypt_key);
-
-static void aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
-{
- struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
- AES_encrypt(src, dst, &ctx->enc_key);
-}
-
-static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
-{
- struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
- AES_decrypt(src, dst, &ctx->dec_key);
-}
-
-static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
- unsigned int key_len)
-{
- struct AES_CTX *ctx = crypto_tfm_ctx(tfm);
-
- switch (key_len) {
- case AES_KEYSIZE_128:
- key_len = 128;
- break;
- case AES_KEYSIZE_192:
- key_len = 192;
- break;
- case AES_KEYSIZE_256:
- key_len = 256;
- break;
- default:
- tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
- return -EINVAL;
- }
-
- if (private_AES_set_encrypt_key(in_key, key_len, &ctx->enc_key) == -1) {
- tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
- return -EINVAL;
- }
- /* private_AES_set_decrypt_key expects an encryption key as input */
- ctx->dec_key = ctx->enc_key;
- if (private_AES_set_decrypt_key(in_key, key_len, &ctx->dec_key) == -1) {
- tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
- return -EINVAL;
- }
- return 0;
-}
-
-static struct crypto_alg aes_alg = {
- .cra_name = "aes",
- .cra_driver_name = "aes-asm",
- .cra_priority = 200,
- .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_ctxsize = sizeof(struct AES_CTX),
- .cra_module = THIS_MODULE,
- .cra_list = LIST_HEAD_INIT(aes_alg.cra_list),
- .cra_u = {
- .cipher = {
- .cia_min_keysize = AES_MIN_KEY_SIZE,
- .cia_max_keysize = AES_MAX_KEY_SIZE,
- .cia_setkey = aes_set_key,
- .cia_encrypt = aes_encrypt,
- .cia_decrypt = aes_decrypt
- }
- }
-};
-
-static int __init aes_init(void)
-{
- return crypto_register_alg(&aes_alg);
-}
-
-static void __exit aes_fini(void)
-{
- crypto_unregister_alg(&aes_alg);
-}
-
-module_init(aes_init);
-module_exit(aes_fini);
-
-MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm (ASM)");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS_CRYPTO("aes");
-MODULE_ALIAS_CRYPTO("aes-asm");
-MODULE_AUTHOR("David McCullough <ucdevel@gmail.com>");
--
2.7.4
^ permalink raw reply related
* Re: Geode LX AES/RNG driver triggers warning
From: David Gstir @ 2017-01-06 13:19 UTC (permalink / raw)
To: PrasannaKumar Muralidharan
Cc: One Thousand Gnomes, linux-geode, linux-crypto, linux-kernel,
teheo, Richard Weinberger
In-Reply-To: <CANc+2y7vh2U_Qrvwof8UZvJqVUL1hc3bQ5qgV-NJQnvQrmQn3Q@mail.gmail.com>
PrasannaKumar,
> On 06.01.2017, at 10:40, PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> wrote:
>
>>> I narrowed it down to commit 6e9b5e76882c ("hwrng: geode - Migrate to managed API") which seems to introduce this. It looks to me like some issue between devres, the Geode hwrng and AES drivers which both use the same PCI device.
>>
>> It does
>>
>>> I'm no expert here, but I curious if this will cause any issues when using the hardware crypto drivers and also what's the best way to get rid of this?
>>
>> Probably to create an mfd device that turns the PCI device into two MFD
>> devices and bind AES and hwrng one to each MFD device. Take a look in
>> drivers/mfd. That would also fix the uglies in mod_init for the rng
>> driver.
>
> I am the author of that commit. Code before commit 6e9b5e76882c had
> ioremap, wondering why there was no warning message before. Just want
> to know if that commit uncovered existing issue or introduced a new
> issue? As far as I understand the commit did not change the
> functionality. Please feel free to correct if I have missed something.
This warning is because commit 6e9b5e76882c introduces devres (devm_ioremap vs ioremap). As soon as I have some spare time, I'll look into resolving this via MFD like Alan suggested.
Thanks,
-David
^ permalink raw reply
* [PATCH] fix itnull.cocci warnings
From: Julia Lawall @ 2017-01-07 9:46 UTC (permalink / raw)
To: Harsh Jain
Cc: hariprasad, netdev, herbert, linux-crypto, Atul Gupta, kbuild-all
The first argument to list_for_each_entry cannot be NULL.
Generated by: scripts/coccinelle/iterators/itnull.cocci
CC: Harsh Jain <harsh@chelsio.com>
Signed-off-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---
This code comes from the following git tree:
url:
https://github.com/0day-ci/linux/commits/Harsh-Jain/crypto-chcr-Bug-fixes/20170107-093356
base:
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
master
In-Reply-To:
<8e0086b56d8fb61637d179c32a09a1bca03c4186.1483599449.git.harsh@chelsio.com>
chcr_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/crypto/chelsio/chcr_core.c
+++ b/drivers/crypto/chelsio/chcr_core.c
@@ -61,7 +61,7 @@ int assign_chcr_device(struct chcr_dev *
*/
mutex_lock(&dev_mutex); /* TODO ? */
list_for_each_entry(u_ctx, &uld_ctx_list, entry)
- if (u_ctx && u_ctx->dev) {
+ if (u_ctx->dev) {
*dev = u_ctx->dev;
ret = 0;
break;
^ permalink raw reply
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