* Re: [PATCH] crypto: loongson - Remove broken and unused loongson-rng
From: Herbert Xu @ 2026-06-11 8:48 UTC (permalink / raw)
To: Eric Biggers
Cc: linux-crypto, linux-kernel, loongarch, Qunqin Zhao, Huacai Chen,
Yinggang Gu, Lee Jones, stable
In-Reply-To: <20260529233208.8703-1-ebiggers@kernel.org>
On Fri, May 29, 2026 at 04:32:08PM -0700, Eric Biggers wrote:
> The loongson-rng rng_alg has several vulnerabilities, including not
> providing forward security, and a use-after-free bug due to the use of
> wait_for_completion_interruptible().
>
> Meanwhile, the rng_alg framework doesn't really have any purpose in the
> first place other than to access the software algorithms crypto/drbg.c
> and crypto/jitterentropy.c. Hardware-specific rng_algs have no
> in-kernel user, and unlike hwrng there's no feed into the actual Linux
> RNG. As such, there's really no point to this code. There are of
> course other rng_alg drivers that are similarly unused, but they're
> similarly in the process of being phased out, e.g.
> https://lore.kernel.org/r/20260529193648.18172-1-ebiggers@kernel.org and
> https://lore.kernel.org/r/20260529220430.34135-1-ebiggers@kernel.org
>
> Given that, there's no point in fixing forward these vulnerabilities,
> and it makes much more sense to simply roll back the addition of this
> driver. If this platform provides TRNG (not PRNG) functionality, it
> could make sense to add a hwrng driver, but it would be quite different.
>
> Link: https://lore.kernel.org/linux-crypto/20260525145939.GC2018@quark/
> Fixes: 766b2d724c8d ("crypto: loongson - add Loongson RNG driver support")
> Cc: stable@vger.kernel.org
> Signed-off-by: Eric Biggers <ebiggers@kernel.org>
> ---
> MAINTAINERS | 1 -
> arch/loongarch/configs/loongson32_defconfig | 1 -
> arch/loongarch/configs/loongson64_defconfig | 1 -
> drivers/crypto/Kconfig | 1 -
> drivers/crypto/Makefile | 1 -
> drivers/crypto/loongson/Kconfig | 6 -
> drivers/crypto/loongson/Makefile | 1 -
> drivers/crypto/loongson/loongson-rng.c | 209 --------------------
> 8 files changed, 221 deletions(-)
> delete mode 100644 drivers/crypto/loongson/Kconfig
> delete mode 100644 drivers/crypto/loongson/Makefile
> delete mode 100644 drivers/crypto/loongson/loongson-rng.c
Patch applied. Thanks.
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH] crypto: crypto4xx - Remove insecure and unused rng_alg
From: Herbert Xu @ 2026-06-11 8:48 UTC (permalink / raw)
To: Eric Biggers
Cc: linux-crypto, Christian Lamparter, linuxppc-dev, linux-kernel,
stable
In-Reply-To: <20260529220430.34135-1-ebiggers@kernel.org>
On Fri, May 29, 2026 at 03:04:30PM -0700, Eric Biggers wrote:
> Remove crypto4xx_rng, as it is insecure and unused:
>
> - It has only a 64-bit security strength, which is highly inadequate.
> This can be seen by the fact that crypto4xx_hw_init() seeds it with
> only 64 bits of entropy, and the fact that the original commit
> mentions that it implements ANSI X9.17 Annex C.
>
> Another issue was that this driver didn't implement the crypto_rng API
> correctly, as crypto4xx_prng_generate() didn't return 0 on success.
>
> - No user of this code is known. It's usable only theoretically via the
> "rng" algorithm type of AF_ALG. But userspace actually just uses the
> actual Linux RNG (/dev/random etc) instead. And rng_algs don't
> contribute entropy to the actual Linux RNG either. (This may have
> been confused with hwrng, which does contribute entropy.)
>
> Fixes: d072bfa48853 ("crypto: crypto4xx - add prng crypto support")
> Cc: stable@vger.kernel.org
> Signed-off-by: Eric Biggers <ebiggers@kernel.org>
> ---
> drivers/crypto/Kconfig | 1 -
> drivers/crypto/amcc/crypto4xx_core.c | 88 -------------------------
> drivers/crypto/amcc/crypto4xx_core.h | 4 --
> drivers/crypto/amcc/crypto4xx_reg_def.h | 11 ----
> 4 files changed, 104 deletions(-)
Patch applied. Thanks.
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH] crypto: qat - validate RSA CRT component lengths
From: Herbert Xu @ 2026-06-11 8:47 UTC (permalink / raw)
To: Giovanni Cabiddu
Cc: linux-crypto, qat-linux, stable, Ahsan Atta, Laurent M Coquerel
In-Reply-To: <20260528155854.40858-1-giovanni.cabiddu@intel.com>
On Thu, May 28, 2026 at 04:57:44PM +0100, Giovanni Cabiddu wrote:
> The generic RSA key parser (rsa_helper.c) bounds each CRT component (p,
> q, dp, dq, qinv) by the modulus size n_sz, but qat_rsa_setkey_crt()
> allocates half-size DMA buffers (key_sz / 2) and right-aligns each
> component with:
>
> memcpy(dst + half_key_sz - len, src, len)
>
> When a CRT component is larger than half_key_sz the subtraction
> underflows and memcpy writes past the DMA buffer, causing memory
> corruption.
>
> Add a len > half_key_sz check next to the existing !len check for each
> of the five CRT components so the driver falls back to the non-CRT path
> instead of writing out of bounds.
>
> Fixes: 879f77e9071f ("crypto: qat - Add RSA CRT mode")
> Cc: stable@vger.kernel.org
> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
> Reviewed-by: Ahsan Atta <ahsan.atta@intel.com>
> Reviewed-by: Laurent M Coquerel <laurent.m.coquerel@intel.com>
> Tested-by: Laurent M Coquerel <laurent.m.coquerel@intel.com>
> ---
> drivers/crypto/intel/qat/qat_common/qat_asym_algs.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
Patch applied. Thanks.
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH v3] hwrng: virtio: clamp device-reported used.len at copy_data()
From: Herbert Xu @ 2026-06-11 7:46 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Michael Bommarito, Olivia Mackall, linux-crypto, Jason Wang,
Kees Cook, Christian Borntraeger, virtualization, linux-kernel,
Dan Williams, Ingo Molnar, H. Peter Anvin, torvalds, alan, tglx
In-Reply-To: <20260611025916-mutt-send-email-mst@kernel.org>
On Thu, Jun 11, 2026 at 03:30:14AM -0400, Michael S. Tsirkin wrote:
> On Thu, Jun 11, 2026 at 12:43:09PM +0800, Herbert Xu wrote:
> > On Sun, May 31, 2026 at 10:22:51AM -0400, Michael Bommarito wrote:
> > >
> > > + size = min_t(unsigned int, size, avail - vi->data_idx);
> > > + idx = array_index_nospec(vi->data_idx, sizeof(vi->data));
> > > + memcpy(buf, vi->data + idx, size);
>
> All the "malicious device" things are confusing. Spectre things -
> doubly so.
>
> So if an access is speculated then CPU might speculate feeding a kernel
> secret into RNG. And then the speculated RNG value maybe can be also
> speculatively be used by some kernel code as an index
> to trigger a cache access, finally leaking the secret?
>
> Maybe?
The way Spectre works is if you have an actual instruction using
idx directly. I don't see how that translates to memcpy.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH v3] hwrng: virtio: clamp device-reported used.len at copy_data()
From: Herbert Xu @ 2026-06-11 8:18 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: Michael Bommarito, Olivia Mackall, linux-crypto, Jason Wang,
Kees Cook, Christian Borntraeger, virtualization, linux-kernel,
Dan Williams, Ingo Molnar, H. Peter Anvin, torvalds, alan, tglx
In-Reply-To: <20260611035035-mutt-send-email-mst@kernel.org>
On Thu, Jun 11, 2026 at 03:58:17AM -0400, Michael S. Tsirkin wrote:
> On Thu, Jun 11, 2026 at 03:46:58PM +0800, Herbert Xu wrote:
> > On Thu, Jun 11, 2026 at 03:30:14AM -0400, Michael S. Tsirkin wrote:
> > > On Thu, Jun 11, 2026 at 12:43:09PM +0800, Herbert Xu wrote:
> > > > On Sun, May 31, 2026 at 10:22:51AM -0400, Michael Bommarito wrote:
> > > > >
> > > > > + size = min_t(unsigned int, size, avail - vi->data_idx);
> > > > > + idx = array_index_nospec(vi->data_idx, sizeof(vi->data));
> > > > > + memcpy(buf, vi->data + idx, size);
> > >
> > > All the "malicious device" things are confusing. Spectre things -
> > > doubly so.
> > >
> > > So if an access is speculated then CPU might speculate feeding a kernel
> > > secret into RNG. And then the speculated RNG value maybe can be also
> > > speculatively be used by some kernel code as an index
> > > to trigger a cache access, finally leaking the secret?
> > >
> > > Maybe?
> >
> > The way Spectre works is if you have an actual instruction using
> > idx directly. I don't see how that translates to memcpy.
>
> I am not sure it has to be direct:
>
> if (malicious_idx > SIZE)
> return;
> src += malicious_idx;
Wait but vi->data_idx isn't even under the hypervisor's control.
It's an index maintained by our own driver. So how can it be
malicious?
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH v3] hwrng: virtio: clamp device-reported used.len at copy_data()
From: Michael S. Tsirkin @ 2026-06-11 7:58 UTC (permalink / raw)
To: Herbert Xu
Cc: Michael Bommarito, Olivia Mackall, linux-crypto, Jason Wang,
Kees Cook, Christian Borntraeger, virtualization, linux-kernel,
Dan Williams, Ingo Molnar, H. Peter Anvin, torvalds, alan, tglx
In-Reply-To: <aipn8sIAQ6Ai2sax@gondor.apana.org.au>
On Thu, Jun 11, 2026 at 03:46:58PM +0800, Herbert Xu wrote:
> On Thu, Jun 11, 2026 at 03:30:14AM -0400, Michael S. Tsirkin wrote:
> > On Thu, Jun 11, 2026 at 12:43:09PM +0800, Herbert Xu wrote:
> > > On Sun, May 31, 2026 at 10:22:51AM -0400, Michael Bommarito wrote:
> > > >
> > > > + size = min_t(unsigned int, size, avail - vi->data_idx);
> > > > + idx = array_index_nospec(vi->data_idx, sizeof(vi->data));
> > > > + memcpy(buf, vi->data + idx, size);
> >
> > All the "malicious device" things are confusing. Spectre things -
> > doubly so.
> >
> > So if an access is speculated then CPU might speculate feeding a kernel
> > secret into RNG. And then the speculated RNG value maybe can be also
> > speculatively be used by some kernel code as an index
> > to trigger a cache access, finally leaking the secret?
> >
> > Maybe?
>
> The way Spectre works is if you have an actual instruction using
> idx directly. I don't see how that translates to memcpy.
I am not sure it has to be direct:
if (malicious_idx > SIZE)
return;
src += malicious_idx;
memcpy(&value, src, ...)
....
hash = complex_hash_of(value)
....
return p[hash * 512];
is IIUC still a valid spectre v1 gadget leaking a value beyong SIZE, or
did I miss something?
And rng is a kind of a complex hash, but I also think in that "...."
in the kernel is probably large enough to close any transient execution
window.
So sure, we can drop this.
> Cheers,
> --
> Email: Herbert Xu <herbert@gondor.apana.org.au>
> Home Page: http://gondor.apana.org.au/~herbert/
> PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* [PATCH v2 19/19] crypto: talitos - Remove TALITOS_DESC_SIZE macro
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Now that TALITOS_DESC_SIZE is simply sizeof(struct talitos_desc) with no
arithmetic, the macro is useless. Replace all occurrences with the
underlying sizeof expression and remove the macro.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 16 ++++++++--------
drivers/crypto/talitos/talitos.h | 2 --
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 1221eb9497fb..7faf3c2606a9 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -166,7 +166,7 @@ static void dma_map_request(struct device *dev, struct talitos_request *request,
if (is_sec1()) {
while (edesc) {
dma_desc = dma_map_single(dev, &edesc->desc.sec1.hdr,
- TALITOS_DESC_SIZE,
+ sizeof(struct talitos_desc),
DMA_BIDIRECTIONAL);
if (!prev_edesc) {
@@ -179,7 +179,7 @@ static void dma_map_request(struct device *dev, struct talitos_request *request,
prev_edesc->desc.sec1.next_desc = cpu_to_be32(dma_desc);
dma_sync_single_for_device(dev, prev_dma_desc,
- TALITOS_DESC_SIZE,
+ sizeof(struct talitos_desc),
DMA_TO_DEVICE);
next:
@@ -188,7 +188,7 @@ static void dma_map_request(struct device *dev, struct talitos_request *request,
edesc = edesc->next_desc;
}
} else {
- request->dma_desc = dma_map_single(dev, desc, TALITOS_DESC_SIZE,
+ request->dma_desc = dma_map_single(dev, desc, sizeof(struct talitos_desc),
DMA_BIDIRECTIONAL);
}
}
@@ -258,7 +258,7 @@ static __be32 get_request_hdr(struct device *dev,
if (!is_sec1()) {
dma_sync_single_for_cpu(dev, request->dma_desc,
- TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
+ sizeof(struct talitos_desc), DMA_BIDIRECTIONAL);
return request->desc->sec2.hdr;
}
@@ -270,7 +270,7 @@ static __be32 get_request_hdr(struct device *dev,
edesc = edesc->next_desc;
}
- dma_sync_single_for_cpu(dev, dma_desc, TALITOS_DESC_SIZE,
+ dma_sync_single_for_cpu(dev, dma_desc, sizeof(struct talitos_desc),
DMA_BIDIRECTIONAL);
return edesc->desc.sec1.hdr;
@@ -282,17 +282,17 @@ static void dma_unmap_request(struct device *dev,
struct talitos_edesc *edesc;
if (is_sec1()) {
- dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
+ dma_unmap_single(dev, request->dma_desc, sizeof(struct talitos_desc),
DMA_BIDIRECTIONAL);
edesc = container_of(request->desc, struct talitos_edesc, desc);
while (edesc->next_desc) {
dma_unmap_single(dev,
be32_to_cpu(edesc->desc.sec1.next_desc),
- TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
+ sizeof(struct talitos_desc), DMA_BIDIRECTIONAL);
edesc = edesc->next_desc;
}
} else {
- dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
+ dma_unmap_single(dev, request->dma_desc, sizeof(struct talitos_desc),
DMA_BIDIRECTIONAL);
}
}
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 2e2414ad1e03..6b9ce69daed4 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -78,8 +78,6 @@ struct talitos_desc {
};
};
-#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc))
-
/*
* talitos_edesc - s/w-extended descriptor
* @bufsl: scatterlist buffer
--
2.54.0
^ permalink raw reply related
* [PATCH v2 18/19] crypto: talitos - Introduce per-SEC-version descriptor and pointer structures
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
The SEC1 and SEC2 hardware descriptor and pointer formats differ in many
ways:
- SEC1 pointers have a 16-bit reserved field followed by a 16-bit length
and 32-bit address, while SEC2 pointers pack a 16-bit length, 8-bit
jump/extent, 8-bit extended address, and 32-bit address.
- SEC1 descriptors chain through a next_desc field absent from SEC2,
while SEC2 has a hdr_lo field that SEC1 lacks.
In the current code, reading those structures and mapping them to the
documentation is not obvious.
Instead of using anonymous union members, define two separate structures
for hardware descriptor and pointer. The counterpart is that some added
helpers are needed.
Even if the structure is naturally aligned and no padding is added, add
the __packed attribute to hint that these structures are used by the
hardware.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-aead.c | 42 +++++-----
drivers/crypto/talitos/talitos-hash.c | 34 ++++----
drivers/crypto/talitos/talitos-skcipher.c | 27 +++---
drivers/crypto/talitos/talitos.c | 20 ++---
drivers/crypto/talitos/talitos.h | 131 +++++++++++++++++++++++-------
5 files changed, 162 insertions(+), 92 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos/talitos-aead.c
index d9e27eddfd1d..667b99581702 100644
--- a/drivers/crypto/talitos/talitos-aead.c
+++ b/drivers/crypto/talitos/talitos-aead.c
@@ -94,11 +94,11 @@ static void ipsec_esp_unmap(struct device *dev,
unsigned int ivsize = crypto_aead_ivsize(aead);
unsigned int authsize = crypto_aead_authsize(aead);
unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
- bool is_ipsec_esp = edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP;
- struct talitos_ptr *civ_ptr = &edesc->desc.ptr[is_ipsec_esp ? 2 : 3];
+ bool is_ipsec_esp = from_talitos_desc_hdr(&edesc->desc) & DESC_HDR_TYPE_IPSEC_ESP;
+ struct talitos_ptr *civ_ptr = from_talitos_desc_ptr(&edesc->desc, is_ipsec_esp ? 2 : 3);
if (is_ipsec_esp)
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6],
+ unmap_single_talitos_ptr(dev, from_talitos_desc_ptr(&edesc->desc, 6),
DMA_FROM_DEVICE);
unmap_single_talitos_ptr(dev, civ_ptr, DMA_TO_DEVICE);
@@ -179,7 +179,7 @@ static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
ipsec_esp_unmap(dev, edesc, req, false);
/* check ICV auth status */
- if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
+ if (!err && ((from_talitos_desc_hdr_lo(desc) & DESC_HDR_LO_ICCR1_MASK) !=
DESC_HDR_LO_ICCR1_PASS))
err = -EBADMSG;
@@ -208,13 +208,13 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
int sg_count, ret;
int elen = 0;
bool sync_needed = false;
- bool is_ipsec_esp = desc->hdr & DESC_HDR_TYPE_IPSEC_ESP;
- struct talitos_ptr *civ_ptr = &desc->ptr[is_ipsec_esp ? 2 : 3];
- struct talitos_ptr *ckey_ptr = &desc->ptr[is_ipsec_esp ? 3 : 2];
+ bool is_ipsec_esp = from_talitos_desc_hdr(desc) & DESC_HDR_TYPE_IPSEC_ESP;
+ struct talitos_ptr *civ_ptr = from_talitos_desc_ptr(desc, is_ipsec_esp ? 2 : 3);
+ struct talitos_ptr *ckey_ptr = from_talitos_desc_ptr(desc, is_ipsec_esp ? 3 : 2);
dma_addr_t dma_icv = edesc->dma_link_tbl + edesc->dma_len - authsize;
/* hmac key */
- to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen);
+ to_talitos_ptr(from_talitos_desc_ptr(desc, 0), ctx->dma_key, ctx->authkeylen);
sg_count = edesc->src_nents ?: 1;
if (is_sec1() && sg_count > 1)
@@ -227,7 +227,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
/* hmac data */
ret = talitos_sg_map(dev, areq->src, areq->assoclen, edesc,
- &desc->ptr[1], sg_count, 0, tbl_off);
+ from_talitos_desc_ptr(desc, 1), sg_count, 0, tbl_off);
if (ret > 1) {
tbl_off += ret;
@@ -247,10 +247,10 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
* extent is bytes of HMAC postpended to ciphertext,
* typically 12 for ipsec
*/
- if (is_ipsec_esp && (desc->hdr & DESC_HDR_MODE1_MDEU_CICV))
+ if (is_ipsec_esp && (from_talitos_desc_hdr(desc) & DESC_HDR_MODE1_MDEU_CICV))
elen = authsize;
- ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4],
+ ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, from_talitos_desc_ptr(desc, 4),
sg_count, areq->assoclen, tbl_off, elen,
false, 1);
@@ -270,7 +270,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
elen = authsize;
else
elen = 0;
- ret = talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, &desc->ptr[5],
+ ret = talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, from_talitos_desc_ptr(desc, 5),
sg_count, areq->assoclen, tbl_off, elen,
is_ipsec_esp && !encrypt, 1);
tbl_off += ret;
@@ -284,19 +284,19 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
/* icv data follows link tables */
to_talitos_ptr(tbl_ptr, dma_icv, authsize);
- to_talitos_ptr_ext_or(&desc->ptr[5], authsize);
+ to_talitos_ptr_ext_or(from_talitos_desc_ptr(desc, 5), authsize);
sync_needed = true;
} else if (!encrypt) {
- to_talitos_ptr(&desc->ptr[6], dma_icv, authsize);
+ to_talitos_ptr(from_talitos_desc_ptr(desc, 6), dma_icv, authsize);
sync_needed = true;
} else if (!is_ipsec_esp) {
- talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6],
+ talitos_sg_map(dev, areq->dst, authsize, edesc, from_talitos_desc_ptr(desc, 6),
sg_count, areq->assoclen + cryptlen, tbl_off);
}
/* iv out */
if (is_ipsec_esp)
- map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
+ map_single_talitos_ptr(dev, from_talitos_desc_ptr(desc, 6), ivsize, ctx->iv,
DMA_FROM_DEVICE);
if (sync_needed)
@@ -339,7 +339,7 @@ static int aead_encrypt(struct aead_request *req)
return PTR_ERR(edesc);
/* set encrypt */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
+ to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT);
return ipsec_esp(edesc, req, true, ipsec_esp_encrypt_done);
}
@@ -358,15 +358,15 @@ static int aead_decrypt(struct aead_request *req)
if (IS_ERR(edesc))
return PTR_ERR(edesc);
- if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) &&
+ if ((from_talitos_desc_hdr(&edesc->desc) & DESC_HDR_TYPE_IPSEC_ESP) &&
(priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
((!edesc->src_nents && !edesc->dst_nents) ||
priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
/* decrypt and check the ICV */
- edesc->desc.hdr = ctx->desc_hdr_template |
+ to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template |
DESC_HDR_DIR_INBOUND |
- DESC_HDR_MODE1_MDEU_CICV;
+ DESC_HDR_MODE1_MDEU_CICV);
/* reset integrity check result bits */
@@ -375,7 +375,7 @@ static int aead_decrypt(struct aead_request *req)
}
/* Have to check the ICV with software */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
+ to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND);
/* stash incoming ICV for later cmp with ICV generated by the h/w */
icvdata = edesc->buf + edesc->dma_len;
diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos/talitos-hash.c
index 8778a2ab812d..7682e1058e7e 100644
--- a/drivers/crypto/talitos/talitos-hash.c
+++ b/drivers/crypto/talitos/talitos-hash.c
@@ -43,7 +43,7 @@ static void common_nonsnoop_hash_unmap(struct device *dev,
struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
struct talitos_desc *desc = &edesc->desc;
- unmap_single_talitos_ptr(dev, &desc->ptr[5], DMA_FROM_DEVICE);
+ unmap_single_talitos_ptr(dev, from_talitos_desc_ptr(desc, 5), DMA_FROM_DEVICE);
if (edesc->last && req_ctx->last_request)
memcpy(areq->result, req_ctx->hw_context,
@@ -53,8 +53,8 @@ static void common_nonsnoop_hash_unmap(struct device *dev,
talitos_sg_unmap(dev, edesc, edesc->src, NULL, 0, 0);
/* When using hashctx-in, must unmap it. */
- if (from_talitos_ptr_len(&desc->ptr[1]))
- unmap_single_talitos_ptr(dev, &desc->ptr[1],
+ if (from_talitos_ptr_len(from_talitos_desc_ptr(desc, 1)))
+ unmap_single_talitos_ptr(dev, from_talitos_desc_ptr(desc, 1),
DMA_TO_DEVICE);
if (edesc->dma_len)
@@ -129,7 +129,7 @@ static void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
};
pr_err_once("Bug in SEC1, padding ourself\n");
- edesc->desc.hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
+ and_talitos_desc_hdr(&edesc->desc, ~DESC_HDR_MODE0_MDEU_PAD);
map_single_talitos_ptr(ctx->dev, ptr, sizeof(padded_hash),
(char *)padded_hash, DMA_TO_DEVICE);
}
@@ -150,7 +150,7 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/* hash context in */
if (!edesc->first || !req_ctx->first_request || req_ctx->swinit) {
- map_single_talitos_ptr_nosync(dev, &desc->ptr[1],
+ map_single_talitos_ptr_nosync(dev, from_talitos_desc_ptr(desc, 1),
req_ctx->hw_context_size,
req_ctx->hw_context,
DMA_TO_DEVICE);
@@ -161,7 +161,7 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/* HMAC key */
if (ctx->keylen)
- to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen);
+ to_talitos_ptr(from_talitos_desc_ptr(desc, 2), ctx->dma_key, ctx->keylen);
sg_count = edesc->src_nents ?: 1;
if (is_sec1() && sg_count > 1)
@@ -172,7 +172,7 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/*
* data in
*/
- sg_count = talitos_sg_map(dev, edesc->src, length, edesc, &desc->ptr[3],
+ sg_count = talitos_sg_map(dev, edesc->src, length, edesc, from_talitos_desc_ptr(desc, 3),
sg_count, 0, 0);
if (sg_count > 1)
sync_needed = true;
@@ -181,19 +181,19 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/* hash/HMAC out -or- hash context out */
if (edesc->last && req_ctx->last_request)
- map_single_talitos_ptr(dev, &desc->ptr[5],
+ map_single_talitos_ptr(dev, from_talitos_desc_ptr(desc, 5),
crypto_ahash_digestsize(tfm),
req_ctx->hw_context, DMA_FROM_DEVICE);
else
- map_single_talitos_ptr_nosync(dev, &desc->ptr[5],
+ map_single_talitos_ptr_nosync(dev, from_talitos_desc_ptr(desc, 5),
req_ctx->hw_context_size,
req_ctx->hw_context,
DMA_FROM_DEVICE);
/* last DWORD empty */
- if (is_sec1() && from_talitos_ptr_len(&desc->ptr[3]) == 0)
- talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
+ if (is_sec1() && from_talitos_ptr_len(from_talitos_desc_ptr(desc, 3)) == 0)
+ talitos_handle_buggy_hash(ctx, edesc, from_talitos_desc_ptr(desc, 3));
if (sync_needed)
dma_sync_single_for_device(dev, edesc->dma_link_tbl,
@@ -240,19 +240,19 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
}
edesc->src = scatterwalk_ffwd(edesc->bufsl, areq->src, offset);
- edesc->desc.hdr = ctx->desc_hdr_template;
+ to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template);
edesc->first = offset == 0;
edesc->last = nbytes - to_hash_this_desc == 0;
/* On last one, request SEC to pad; otherwise continue */
if (req_ctx->last_request && edesc->last)
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
+ or_talitos_desc_hdr(&edesc->desc, DESC_HDR_MODE0_MDEU_PAD);
else
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
+ or_talitos_desc_hdr(&edesc->desc, DESC_HDR_MODE0_MDEU_CONT);
/* request SEC to INIT hash. */
if (req_ctx->first_request && edesc->first && !req_ctx->swinit)
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
+ or_talitos_desc_hdr(&edesc->desc, DESC_HDR_MODE0_MDEU_INIT);
/*
* When the tfm context has a keylen, it's an HMAC.
@@ -260,11 +260,11 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
*/
if (ctx->keylen && ((req_ctx->first_request && edesc->first) ||
(req_ctx->last_request && edesc->last)))
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
+ or_talitos_desc_hdr(&edesc->desc, DESC_HDR_MODE0_MDEU_HMAC);
/* clear the DN bit */
if (is_sec1() && !edesc->last)
- edesc->desc.hdr &= ~DESC_HDR_DONE_NOTIFY;
+ and_talitos_desc_hdr(&edesc->desc, ~DESC_HDR_DONE_NOTIFY);
common_nonsnoop_hash(edesc, areq, to_hash_this_desc);
diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/talitos/talitos-skcipher.c
index 2c34e2ffbf7e..79317fb7f47e 100644
--- a/drivers/crypto/talitos/talitos-skcipher.c
+++ b/drivers/crypto/talitos/talitos-skcipher.c
@@ -15,10 +15,10 @@ static void common_nonsnoop_unmap(struct device *dev,
struct talitos_edesc *edesc,
struct skcipher_request *areq)
{
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
+ unmap_single_talitos_ptr(dev, from_talitos_desc_ptr(&edesc->desc, 5), DMA_FROM_DEVICE);
talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen, 0);
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
+ unmap_single_talitos_ptr(dev, from_talitos_desc_ptr(&edesc->desc, 1), DMA_TO_DEVICE);
if (edesc->dma_len)
dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
@@ -59,16 +59,18 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
unsigned int ivsize = crypto_skcipher_ivsize(cipher);
int sg_count, ret;
bool sync_needed = false;
- bool is_ctr = (desc->hdr & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_AESU &&
- (desc->hdr & DESC_HDR_MODE0_AESU_MASK) == DESC_HDR_MODE0_AESU_CTR;
+ bool is_ctr = (from_talitos_desc_hdr(desc) & DESC_HDR_SEL0_MASK) ==
+ DESC_HDR_SEL0_AESU &&
+ (from_talitos_desc_hdr(desc) &
+ DESC_HDR_MODE0_AESU_MASK) == DESC_HDR_MODE0_AESU_CTR;
/* first DWORD empty */
/* cipher iv */
- to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize);
+ to_talitos_ptr(from_talitos_desc_ptr(desc, 1), edesc->iv_dma, ivsize);
/* cipher key */
- to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen);
+ to_talitos_ptr(from_talitos_desc_ptr(desc, 2), ctx->dma_key, ctx->keylen);
sg_count = edesc->src_nents ?: 1;
if (is_sec1() && sg_count > 1)
@@ -81,8 +83,9 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/*
* cipher in
*/
- sg_count = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[3],
- sg_count, 0, 0, 0, false, is_ctr ? 16 : 1);
+ sg_count = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc,
+ from_talitos_desc_ptr(desc, 3), sg_count,
+ 0, 0, 0, false, is_ctr ? 16 : 1);
if (sg_count > 1)
sync_needed = true;
@@ -93,13 +96,13 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
}
- ret = talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[4],
+ ret = talitos_sg_map(dev, areq->dst, cryptlen, edesc, from_talitos_desc_ptr(desc, 4),
sg_count, 0, (edesc->src_nents + 1));
if (ret > 1)
sync_needed = true;
/* iv out */
- map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv,
+ map_single_talitos_ptr(dev, from_talitos_desc_ptr(desc, 5), ivsize, ctx->iv,
DMA_FROM_DEVICE);
/* last DWORD empty */
@@ -189,7 +192,7 @@ static int skcipher_encrypt(struct skcipher_request *areq)
return PTR_ERR(edesc);
/* set encrypt */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
+ to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT);
return common_nonsnoop(edesc, areq, skcipher_done);
}
@@ -213,7 +216,7 @@ static int skcipher_decrypt(struct skcipher_request *areq)
if (IS_ERR(edesc))
return PTR_ERR(edesc);
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
+ to_talitos_desc_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND);
return common_nonsnoop(edesc, areq, skcipher_done);
}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 8ea26422f449..1221eb9497fb 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -165,9 +165,7 @@ static void dma_map_request(struct device *dev, struct talitos_request *request,
if (is_sec1()) {
while (edesc) {
- edesc->desc.hdr1 = edesc->desc.hdr;
-
- dma_desc = dma_map_single(dev, &edesc->desc.hdr1,
+ dma_desc = dma_map_single(dev, &edesc->desc.sec1.hdr,
TALITOS_DESC_SIZE,
DMA_BIDIRECTIONAL);
@@ -178,7 +176,7 @@ static void dma_map_request(struct device *dev, struct talitos_request *request,
/* Chain in any previous descriptors. */
- prev_edesc->desc.next_desc = cpu_to_be32(dma_desc);
+ prev_edesc->desc.sec1.next_desc = cpu_to_be32(dma_desc);
dma_sync_single_for_device(dev, prev_dma_desc,
TALITOS_DESC_SIZE,
@@ -262,20 +260,20 @@ static __be32 get_request_hdr(struct device *dev,
dma_sync_single_for_cpu(dev, request->dma_desc,
TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
- return request->desc->hdr;
+ return request->desc->sec2.hdr;
}
edesc = container_of(request->desc, struct talitos_edesc, desc);
dma_desc = request->dma_desc;
while (edesc->next_desc) {
- dma_desc = be32_to_cpu(edesc->desc.next_desc);
+ dma_desc = be32_to_cpu(edesc->desc.sec1.next_desc);
edesc = edesc->next_desc;
}
dma_sync_single_for_cpu(dev, dma_desc, TALITOS_DESC_SIZE,
DMA_BIDIRECTIONAL);
- return edesc->desc.hdr1;
+ return edesc->desc.sec1.hdr;
}
static void dma_unmap_request(struct device *dev,
@@ -289,7 +287,7 @@ static void dma_unmap_request(struct device *dev,
edesc = container_of(request->desc, struct talitos_edesc, desc);
while (edesc->next_desc) {
dma_unmap_single(dev,
- be32_to_cpu(edesc->desc.next_desc),
+ be32_to_cpu(edesc->desc.sec1.next_desc),
TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
edesc = edesc->next_desc;
}
@@ -424,12 +422,12 @@ static __be32 search_desc_hdr_in_request(struct talitos_request *request,
struct talitos_edesc *edesc;
if (request->dma_desc == cur_desc) {
- return request->desc->hdr;
+ return from_talitos_desc_hdr(request->desc);
} else if (is_sec1()) {
edesc = container_of(request->desc, struct talitos_edesc, desc);
while (edesc->next_desc) {
- if (edesc->desc.next_desc == cpu_to_be32(cur_desc))
- return edesc->next_desc->desc.hdr1;
+ if (edesc->desc.sec1.next_desc == cpu_to_be32(cur_desc))
+ return edesc->next_desc->desc.sec1.hdr;
edesc = edesc->next_desc;
}
}
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 9bbdd409da5a..2e2414ad1e03 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -36,33 +36,49 @@
#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
/* descriptor pointer entry */
+
+struct sec1_talitos_ptr {
+ __be16 res;
+ __be16 len;
+ __be32 ptr;
+} __packed;
+
+struct sec2_talitos_ptr {
+ __be16 len;
+ u8 j_extent;
+ u8 eptr;
+ __be32 ptr;
+} __packed;
+
struct talitos_ptr {
union {
- struct { /* SEC2 format */
- __be16 len; /* length */
- u8 j_extent; /* jump to sg link table and/or extent*/
- u8 eptr; /* extended address */
- };
- struct { /* SEC1 format */
- __be16 res;
- __be16 len1; /* length */
- };
+ struct sec1_talitos_ptr sec1;
+ struct sec2_talitos_ptr sec2;
};
- __be32 ptr; /* address */
};
-/* descriptor */
+/* descriptor format */
+
+struct sec1_talitos_desc {
+ __be32 hdr;
+ struct sec1_talitos_ptr ptr[7];
+ __be32 next_desc;
+} __packed;
+
+struct sec2_talitos_desc {
+ __be32 hdr;
+ __be32 hdr_lo;
+ struct sec2_talitos_ptr ptr[7];
+} __packed;
+
struct talitos_desc {
- __be32 hdr; /* header high bits */
union {
- __be32 hdr_lo; /* header low bits */
- __be32 hdr1; /* header for SEC1 */
+ struct sec1_talitos_desc sec1;
+ struct sec2_talitos_desc sec2;
};
- struct talitos_ptr ptr[7]; /* ptr/len pair array */
- __be32 next_desc; /* next descriptor (SEC1) */
};
-#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
+#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc))
/*
* talitos_edesc - s/w-extended descriptor
@@ -488,48 +504,101 @@ static inline void talitos_init_branch(bool sec1)
#define DESC_PTR_LNKTBL_RET 0x02
#define DESC_PTR_LNKTBL_NEXT 0x01
+static inline __be32 from_talitos_ptr(struct talitos_ptr *ptr)
+{
+ if (is_sec1())
+ return ptr->sec1.ptr;
+ return ptr->sec2.ptr;
+}
+
+static inline __be32 from_talitos_desc_hdr(struct talitos_desc *desc)
+{
+ if (is_sec1())
+ return desc->sec1.hdr;
+ return desc->sec2.hdr;
+}
+
+static inline void to_talitos_desc_hdr(struct talitos_desc *desc, __be32 val)
+{
+ if (is_sec1())
+ desc->sec1.hdr = val;
+ else
+ desc->sec2.hdr = val;
+}
+
+static inline void or_talitos_desc_hdr(struct talitos_desc *desc, __be32 val)
+{
+ if (is_sec1())
+ desc->sec1.hdr |= val;
+ else
+ desc->sec2.hdr |= val;
+}
+
+static inline void and_talitos_desc_hdr(struct talitos_desc *desc, __be32 val)
+{
+ if (is_sec1())
+ desc->sec1.hdr &= val;
+ else
+ desc->sec2.hdr &= val;
+}
+
+static inline __be32 from_talitos_desc_hdr_lo(struct talitos_desc *desc)
+{
+ return desc->sec2.hdr_lo;
+}
+
+static inline struct talitos_ptr *
+from_talitos_desc_ptr(struct talitos_desc *desc, int idx)
+{
+ if (is_sec1())
+ return (struct talitos_ptr *)&desc->sec1.ptr[idx];
+ return (struct talitos_ptr *)&desc->sec2.ptr[idx];
+}
+
static inline void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
unsigned int len)
{
- ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
if (is_sec1()) {
- ptr->len1 = cpu_to_be16(len);
+ ptr->sec1.ptr = cpu_to_be32(lower_32_bits(dma_addr));
+ ptr->sec1.len = cpu_to_be16(len);
} else {
- ptr->len = cpu_to_be16(len);
- ptr->eptr = upper_32_bits(dma_addr);
+ ptr->sec2.ptr = cpu_to_be32(lower_32_bits(dma_addr));
+ ptr->sec2.len = cpu_to_be16(len);
+ ptr->sec2.eptr = upper_32_bits(dma_addr);
}
}
static inline void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
struct talitos_ptr *src_ptr)
{
- dst_ptr->ptr = src_ptr->ptr;
if (is_sec1()) {
- dst_ptr->len1 = src_ptr->len1;
+ dst_ptr->sec1.ptr = src_ptr->sec1.ptr;
+ dst_ptr->sec1.len = src_ptr->sec1.len;
} else {
- dst_ptr->len = src_ptr->len;
- dst_ptr->eptr = src_ptr->eptr;
+ dst_ptr->sec2.ptr = src_ptr->sec2.ptr;
+ dst_ptr->sec2.len = src_ptr->sec2.len;
+ dst_ptr->sec2.eptr = src_ptr->sec2.eptr;
}
}
static inline unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr)
{
if (is_sec1())
- return be16_to_cpu(ptr->len1);
+ return be16_to_cpu(ptr->sec1.len);
else
- return be16_to_cpu(ptr->len);
+ return be16_to_cpu(ptr->sec2.len);
}
static inline void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val)
{
if (!is_sec1())
- ptr->j_extent = val;
+ ptr->sec2.j_extent = val;
}
static inline void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val)
{
if (!is_sec1())
- ptr->j_extent |= val;
+ ptr->sec2.j_extent |= val;
}
/*
@@ -569,8 +638,8 @@ static inline void unmap_single_talitos_ptr(struct device *dev,
struct talitos_ptr *ptr,
enum dma_data_direction dir)
{
- dma_unmap_single(dev, be32_to_cpu(ptr->ptr), from_talitos_ptr_len(ptr),
- dir);
+ dma_unmap_single(dev, be32_to_cpu(from_talitos_ptr(ptr)),
+ from_talitos_ptr_len(ptr), dir);
}
int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
--
2.54.0
^ permalink raw reply related
* [PATCH v2 17/19] crypto: talitos - Replace has_ftr_sec1() with is_sec1() static key helper
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Now that is_sec1() is available, replace all has_ftr_sec1(priv) calls
and the local "bool is_sec1" variables with direct is_sec1()
invocations.
It removes the requirement that every caller has to either get struct
talitos_private out of dev_get_drvdata() or/and pass the is_sec1
parameter to each inline helper.
Drop the now-unused has_ftr_sec1() helper.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-aead.c | 24 +++----
drivers/crypto/talitos/talitos-hash.c | 26 +++----
drivers/crypto/talitos/talitos-skcipher.c | 15 ++--
drivers/crypto/talitos/talitos.c | 113 +++++++++++++-----------------
drivers/crypto/talitos/talitos.h | 49 ++++---------
5 files changed, 87 insertions(+), 140 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos/talitos-aead.c
index cd1b8e6d371b..d9e27eddfd1d 100644
--- a/drivers/crypto/talitos/talitos-aead.c
+++ b/drivers/crypto/talitos/talitos-aead.c
@@ -208,18 +208,16 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
int sg_count, ret;
int elen = 0;
bool sync_needed = false;
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
bool is_ipsec_esp = desc->hdr & DESC_HDR_TYPE_IPSEC_ESP;
struct talitos_ptr *civ_ptr = &desc->ptr[is_ipsec_esp ? 2 : 3];
struct talitos_ptr *ckey_ptr = &desc->ptr[is_ipsec_esp ? 3 : 2];
dma_addr_t dma_icv = edesc->dma_link_tbl + edesc->dma_len - authsize;
/* hmac key */
- to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen, is_sec1);
+ to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen);
sg_count = edesc->src_nents ?: 1;
- if (is_sec1 && sg_count > 1)
+ if (is_sec1() && sg_count > 1)
sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
areq->assoclen + cryptlen);
else
@@ -237,11 +235,11 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
}
/* cipher iv */
- to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize, is_sec1);
+ to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize);
/* cipher key */
to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen,
- ctx->enckeylen, is_sec1);
+ ctx->enckeylen);
/*
* cipher in
@@ -264,7 +262,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
/* cipher out */
if (areq->src != areq->dst) {
sg_count = edesc->dst_nents ? : 1;
- if (!is_sec1 || sg_count == 1)
+ if (!is_sec1() || sg_count == 1)
dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
}
@@ -281,15 +279,15 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
/* Add an entry to the link table for ICV data */
- to_talitos_ptr_ext_set(tbl_ptr - 1, 0, is_sec1);
- to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET, is_sec1);
+ to_talitos_ptr_ext_set(tbl_ptr - 1, 0);
+ to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET);
/* icv data follows link tables */
- to_talitos_ptr(tbl_ptr, dma_icv, authsize, is_sec1);
- to_talitos_ptr_ext_or(&desc->ptr[5], authsize, is_sec1);
+ to_talitos_ptr(tbl_ptr, dma_icv, authsize);
+ to_talitos_ptr_ext_or(&desc->ptr[5], authsize);
sync_needed = true;
} else if (!encrypt) {
- to_talitos_ptr(&desc->ptr[6], dma_icv, authsize, is_sec1);
+ to_talitos_ptr(&desc->ptr[6], dma_icv, authsize);
sync_needed = true;
} else if (!is_ipsec_esp) {
talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6],
@@ -642,7 +640,7 @@ int talitos_register_aead(struct device *dev)
aead_alg = &aead_driver_algs[i].alg.aead;
alg = &aead_alg->base;
- if (has_ftr_sec1(priv))
+ if (is_sec1())
alg->cra_alignmask = 3;
if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos/talitos-hash.c
index f3bffb0fdd2e..8778a2ab812d 100644
--- a/drivers/crypto/talitos/talitos-hash.c
+++ b/drivers/crypto/talitos/talitos-hash.c
@@ -41,8 +41,6 @@ static void common_nonsnoop_hash_unmap(struct device *dev,
{
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
struct talitos_desc *desc = &edesc->desc;
unmap_single_talitos_ptr(dev, &desc->ptr[5], DMA_FROM_DEVICE);
@@ -55,7 +53,7 @@ static void common_nonsnoop_hash_unmap(struct device *dev,
talitos_sg_unmap(dev, edesc, edesc->src, NULL, 0, 0);
/* When using hashctx-in, must unmap it. */
- if (from_talitos_ptr_len(&desc->ptr[1], is_sec1))
+ if (from_talitos_ptr_len(&desc->ptr[1]))
unmap_single_talitos_ptr(dev, &desc->ptr[1],
DMA_TO_DEVICE);
@@ -86,11 +84,10 @@ static void ahash_done(struct device *dev,
container_of(desc, struct talitos_edesc, desc);
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- bool is_sec1 = has_ftr_sec1(dev_get_drvdata(dev));
struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
struct talitos_edesc *next;
- if (is_sec1) {
+ if (is_sec1()) {
free_edesc_list_from(areq, edesc);
ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
} else {
@@ -147,8 +144,6 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
struct device *dev = ctx->dev;
struct talitos_desc *desc = &edesc->desc;
bool sync_needed = false;
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
int sg_count;
/* first DWORD empty */
@@ -166,11 +161,10 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/* HMAC key */
if (ctx->keylen)
- to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen,
- is_sec1);
+ to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen);
sg_count = edesc->src_nents ?: 1;
- if (is_sec1 && sg_count > 1)
+ if (is_sec1() && sg_count > 1)
sg_copy_to_buffer(edesc->src, sg_count, edesc->buf, length);
else if (length)
sg_count = dma_map_sg(dev, edesc->src, sg_count, DMA_TO_DEVICE);
@@ -198,7 +192,7 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/* last DWORD empty */
- if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) == 0)
+ if (is_sec1() && from_talitos_ptr_len(&desc->ptr[3]) == 0)
talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
if (sync_needed)
@@ -219,12 +213,12 @@ static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
static struct talitos_edesc *
ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
- unsigned int blocksize, bool is_sec1)
+ unsigned int blocksize)
{
struct talitos_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
struct talitos_edesc *first = NULL, *prev_edesc = NULL, *edesc;
- size_t desc_max = is_sec1 ? TALITOS1_MAX_DATA_LEN :
+ size_t desc_max = is_sec1() ? TALITOS1_MAX_DATA_LEN :
TALITOS2_MAX_DATA_LEN;
struct scatterlist tmp[2];
size_t to_hash_this_desc;
@@ -269,7 +263,7 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
/* clear the DN bit */
- if (is_sec1 && !edesc->last)
+ if (is_sec1() && !edesc->last)
edesc->desc.hdr &= ~DESC_HDR_DONE_NOTIFY;
common_nonsnoop_hash(edesc, areq, to_hash_this_desc);
@@ -295,7 +289,6 @@ static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
struct talitos_edesc *edesc;
unsigned int blocksize =
crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
- bool is_sec1 = has_ftr_sec1(dev_get_drvdata(ctx->dev));
unsigned int nbytes_to_hash;
unsigned int to_hash_later;
struct device *dev = ctx->dev;
@@ -311,8 +304,7 @@ static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
req_ctx->to_hash_later = to_hash_later;
- edesc = ahash_process_req_prepare(areq, nbytes_to_hash, blocksize,
- is_sec1);
+ edesc = ahash_process_req_prepare(areq, nbytes_to_hash, blocksize);
if (IS_ERR(edesc))
return PTR_ERR(edesc);
diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/talitos/talitos-skcipher.c
index b12191243aae..2c34e2ffbf7e 100644
--- a/drivers/crypto/talitos/talitos-skcipher.c
+++ b/drivers/crypto/talitos/talitos-skcipher.c
@@ -59,21 +59,19 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
unsigned int ivsize = crypto_skcipher_ivsize(cipher);
int sg_count, ret;
bool sync_needed = false;
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
bool is_ctr = (desc->hdr & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_AESU &&
(desc->hdr & DESC_HDR_MODE0_AESU_MASK) == DESC_HDR_MODE0_AESU_CTR;
/* first DWORD empty */
/* cipher iv */
- to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize, is_sec1);
+ to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize);
/* cipher key */
- to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, is_sec1);
+ to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen);
sg_count = edesc->src_nents ?: 1;
- if (is_sec1 && sg_count > 1)
+ if (is_sec1() && sg_count > 1)
sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
cryptlen);
else
@@ -91,7 +89,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/* cipher out */
if (areq->src != areq->dst) {
sg_count = edesc->dst_nents ? : 1;
- if (!is_sec1 || sg_count == 1)
+ if (!is_sec1() || sg_count == 1)
dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
}
@@ -324,7 +322,6 @@ static struct talitos_alg_template skcipher_driver_algs[] = {
int talitos_register_skcipher(struct device *dev)
{
- struct talitos_private *priv = dev_get_drvdata(dev);
struct skcipher_alg *skcipher_alg;
struct crypto_alg *alg;
size_t i;
@@ -338,10 +335,10 @@ int talitos_register_skcipher(struct device *dev)
skcipher_alg = &skcipher_driver_algs[i].alg.skcipher;
alg = &skcipher_alg->base;
- if (has_ftr_sec1(priv))
+ if (is_sec1())
alg->cra_alignmask = 3;
- if (!strcmp(alg->cra_name, "ctr(aes)") && !has_ftr_sec1(priv) &&
+ if (!strcmp(alg->cra_name, "ctr(aes)") && !is_sec1() &&
DESC_TYPE(skcipher_driver_algs[i].desc_hdr_template) !=
DESC_TYPE(DESC_HDR_TYPE_AESU_CTR_NONSNOOP)) {
continue;
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index c93e3b551f6d..8ea26422f449 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -44,9 +44,8 @@ static int reset_channel(struct device *dev, int ch)
{
struct talitos_private *priv = dev_get_drvdata(dev);
unsigned int timeout = TALITOS_TIMEOUT;
- bool is_sec1 = has_ftr_sec1(priv);
- if (is_sec1) {
+ if (is_sec1()) {
setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
TALITOS1_CCCR_LO_RESET);
@@ -71,7 +70,7 @@ static int reset_channel(struct device *dev, int ch)
setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
/* enable chaining descriptors */
- if (is_sec1)
+ if (is_sec1())
setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
TALITOS_CCCR_LO_NE);
@@ -87,8 +86,7 @@ static int reset_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
unsigned int timeout = TALITOS_TIMEOUT;
- bool is_sec1 = has_ftr_sec1(priv);
- u32 mcr = is_sec1 ? TALITOS1_MCR_SWR : TALITOS2_MCR_SWR;
+ u32 mcr = is_sec1() ? TALITOS1_MCR_SWR : TALITOS2_MCR_SWR;
setbits32(priv->reg + TALITOS_MCR, mcr);
@@ -116,7 +114,6 @@ static int init_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
int ch, err;
- bool is_sec1 = has_ftr_sec1(priv);
/*
* Master reset
@@ -140,7 +137,7 @@ static int init_device(struct device *dev)
}
/* enable channel done and error interrupts */
- if (is_sec1) {
+ if (is_sec1()) {
clrbits32(priv->reg + TALITOS_IMR, TALITOS1_IMR_INIT);
clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);
/* disable parity error check in DEU (erroneous? test vect.) */
@@ -159,14 +156,14 @@ static int init_device(struct device *dev)
}
static void dma_map_request(struct device *dev, struct talitos_request *request,
- struct talitos_desc *desc, bool is_sec1)
+ struct talitos_desc *desc)
{
struct talitos_edesc *edesc =
container_of(desc, struct talitos_edesc, desc);
dma_addr_t dma_desc, prev_dma_desc;
struct talitos_edesc *prev_edesc = NULL;
- if (is_sec1) {
+ if (is_sec1()) {
while (edesc) {
edesc->desc.hdr1 = edesc->desc.hdr;
@@ -220,7 +217,6 @@ int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
struct talitos_request *request;
unsigned long flags;
int head;
- bool is_sec1 = has_ftr_sec1(priv);
spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
@@ -234,7 +230,7 @@ int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
request = &priv->chan[ch].fifo[head];
/* map descriptor and save caller data */
- dma_map_request(dev, request, desc, is_sec1);
+ dma_map_request(dev, request, desc);
request->callback = callback;
request->context = context;
@@ -257,12 +253,12 @@ int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
}
static __be32 get_request_hdr(struct device *dev,
- struct talitos_request *request, bool is_sec1)
+ struct talitos_request *request)
{
struct talitos_edesc *edesc;
dma_addr_t dma_desc;
- if (!is_sec1) {
+ if (!is_sec1()) {
dma_sync_single_for_cpu(dev, request->dma_desc,
TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
@@ -283,11 +279,11 @@ static __be32 get_request_hdr(struct device *dev,
}
static void dma_unmap_request(struct device *dev,
- struct talitos_request *request, bool is_sec1)
+ struct talitos_request *request)
{
struct talitos_edesc *edesc;
- if (is_sec1) {
+ if (is_sec1()) {
dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
DMA_BIDIRECTIONAL);
edesc = container_of(request->desc, struct talitos_edesc, desc);
@@ -312,7 +308,6 @@ static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
struct talitos_request *request, saved_req;
unsigned long flags;
int tail, status;
- bool is_sec1 = has_ftr_sec1(priv);
spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
@@ -324,7 +319,7 @@ static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
/* descriptors with their done bits set don't get the error */
rmb();
- hdr = get_request_hdr(dev, request, is_sec1);
+ hdr = get_request_hdr(dev, request);
if ((hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
status = 0;
@@ -334,7 +329,7 @@ static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
else
status = error;
- dma_unmap_request(dev, request, is_sec1);
+ dma_unmap_request(dev, request);
/* copy entries so we can call callback outside lock */
saved_req.desc = request->desc;
@@ -424,13 +419,13 @@ DEF_TALITOS2_DONE(ch0_2, TALITOS2_ISR_CH_0_2_DONE)
DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE)
static __be32 search_desc_hdr_in_request(struct talitos_request *request,
- dma_addr_t cur_desc, bool is_sec1)
+ dma_addr_t cur_desc)
{
struct talitos_edesc *edesc;
if (request->dma_desc == cur_desc) {
return request->desc->hdr;
- } else if (is_sec1) {
+ } else if (is_sec1()) {
edesc = container_of(request->desc, struct talitos_edesc, desc);
while (edesc->next_desc) {
if (edesc->desc.next_desc == cpu_to_be32(cur_desc))
@@ -447,7 +442,6 @@ static __be32 search_desc_hdr_in_request(struct talitos_request *request,
static __be32 current_desc_hdr(struct device *dev, int ch)
{
struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
struct talitos_request *request;
int tail, iter;
dma_addr_t cur_desc;
@@ -466,7 +460,7 @@ static __be32 current_desc_hdr(struct device *dev, int ch)
do {
request = &priv->chan[ch].fifo[iter];
- hdr = search_desc_hdr_in_request(request, cur_desc, is_sec1);
+ hdr = search_desc_hdr_in_request(request, cur_desc);
if (hdr)
break;
@@ -563,12 +557,11 @@ static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
unsigned int timeout = TALITOS_TIMEOUT;
int ch, error, reset_dev = 0;
u32 v_lo;
- bool is_sec1 = has_ftr_sec1(priv);
- int reset_ch = is_sec1 ? 1 : 0; /* only SEC2 supports continuation */
+ int reset_ch = is_sec1() ? 1 : 0; /* only SEC2 supports continuation */
for (ch = 0; ch < priv->num_channels; ch++) {
/* skip channels without errors */
- if (is_sec1) {
+ if (is_sec1()) {
/* bits 29, 31, 17, 19 */
if (!(isr & (1 << (29 + (ch & 1) * 2 - (ch & 2) * 6))))
continue;
@@ -594,19 +587,19 @@ static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
if (v_lo & TALITOS_CCPSR_LO_MDTE)
dev_err(dev, "master data transfer error\n");
if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
- dev_err(dev, is_sec1 ? "pointer not complete error\n"
+ dev_err(dev, is_sec1() ? "pointer not complete error\n"
: "s/g data length zero error\n");
if (v_lo & TALITOS_CCPSR_LO_FPZ)
- dev_err(dev, is_sec1 ? "parity error\n"
+ dev_err(dev, is_sec1() ? "parity error\n"
: "fetch pointer zero error\n");
if (v_lo & TALITOS_CCPSR_LO_IDH)
dev_err(dev, "illegal descriptor header error\n");
if (v_lo & TALITOS_CCPSR_LO_IEU)
- dev_err(dev, is_sec1 ? "static assignment error\n"
+ dev_err(dev, is_sec1() ? "static assignment error\n"
: "invalid exec unit error\n");
if (v_lo & TALITOS_CCPSR_LO_EU)
report_eu_error(dev, ch, current_desc_hdr(dev, ch));
- if (!is_sec1) {
+ if (!is_sec1()) {
if (v_lo & TALITOS_CCPSR_LO_GB)
dev_err(dev, "gather boundary error\n");
if (v_lo & TALITOS_CCPSR_LO_GRL)
@@ -635,9 +628,9 @@ static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
}
}
}
- if (reset_dev || (is_sec1 && isr & ~TALITOS1_ISR_4CHERR) ||
- (!is_sec1 && isr & ~TALITOS2_ISR_4CHERR) || isr_lo) {
- if (is_sec1 && (isr_lo & TALITOS1_ISR_TEA_ERR))
+ if (reset_dev || (is_sec1() && isr & ~TALITOS1_ISR_4CHERR) ||
+ (!is_sec1() && isr & ~TALITOS2_ISR_4CHERR) || isr_lo) {
+ if (is_sec1() && (isr_lo & TALITOS1_ISR_TEA_ERR))
dev_err(dev, "TEA error: ISR 0x%08x_%08x\n",
isr, isr_lo);
else
@@ -733,24 +726,22 @@ void talitos_sg_unmap(struct device *dev,
struct scatterlist *dst,
unsigned int len, unsigned int offset)
{
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
unsigned int src_nents = edesc->src_nents ? : 1;
unsigned int dst_nents = edesc->dst_nents ? : 1;
- if (is_sec1 && dst && dst_nents > 1) {
+ if (is_sec1() && dst && dst_nents > 1) {
dma_sync_single_for_device(dev, edesc->dma_link_tbl + offset,
len, DMA_FROM_DEVICE);
sg_pcopy_from_buffer(dst, dst_nents, edesc->buf + offset, len,
offset);
}
if (src != dst) {
- if (src_nents == 1 || !is_sec1)
+ if (src_nents == 1 || !is_sec1())
dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
- if (dst && (dst_nents == 1 || !is_sec1))
+ if (dst && (dst_nents == 1 || !is_sec1()))
dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
- } else if (src_nents == 1 || !is_sec1) {
+ } else if (src_nents == 1 || !is_sec1()) {
dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
}
}
@@ -783,15 +774,15 @@ static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
if (datalen > 0 && len > datalen) {
to_talitos_ptr(link_tbl_ptr + count,
- sg_dma_address(sg) + offset, datalen, 0);
- to_talitos_ptr_ext_set(link_tbl_ptr + count, 0, 0);
+ sg_dma_address(sg) + offset, datalen);
+ to_talitos_ptr_ext_set(link_tbl_ptr + count, 0);
count++;
len -= datalen;
offset += datalen;
}
to_talitos_ptr(link_tbl_ptr + count,
- sg_dma_address(sg) + offset, sg_next(sg) ? len : len + padding, 0);
- to_talitos_ptr_ext_set(link_tbl_ptr + count, 0, 0);
+ sg_dma_address(sg) + offset, sg_next(sg) ? len : len + padding);
+ to_talitos_ptr_ext_set(link_tbl_ptr + count, 0);
count++;
cryptlen -= len;
datalen -= len;
@@ -804,7 +795,7 @@ static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
/* tag end of link table */
if (count > 0)
to_talitos_ptr_ext_set(link_tbl_ptr + count - 1,
- DESC_PTR_LNKTBL_RET, 0);
+ DESC_PTR_LNKTBL_RET);
return count;
}
@@ -815,33 +806,30 @@ int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
unsigned int offset, int tbl_off, int elen,
bool force, int align)
{
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
int aligned_len = ALIGN(len, align);
if (!src) {
- to_talitos_ptr(ptr, 0, 0, is_sec1);
+ to_talitos_ptr(ptr, 0, 0);
return 1;
}
- to_talitos_ptr_ext_set(ptr, elen, is_sec1);
+ to_talitos_ptr_ext_set(ptr, elen);
if (sg_count == 1 && !force) {
- to_talitos_ptr(ptr, sg_dma_address(src) + offset, aligned_len, is_sec1);
+ to_talitos_ptr(ptr, sg_dma_address(src) + offset, aligned_len);
return sg_count;
}
- if (is_sec1) {
- to_talitos_ptr(ptr, edesc->dma_link_tbl + offset, aligned_len, is_sec1);
+ if (is_sec1()) {
+ to_talitos_ptr(ptr, edesc->dma_link_tbl + offset, aligned_len);
return sg_count;
}
sg_count = sg_to_link_tbl_offset(src, sg_count, offset, len, elen,
&edesc->link_tbl[tbl_off], align);
if (sg_count == 1 && !force) {
- /* Only one segment now, so no link tbl needed*/
- copy_talitos_ptr(ptr, &edesc->link_tbl[tbl_off], is_sec1);
+ copy_talitos_ptr(ptr, &edesc->link_tbl[tbl_off]);
return sg_count;
}
to_talitos_ptr(ptr, edesc->dma_link_tbl +
- tbl_off * sizeof(struct talitos_ptr), aligned_len, is_sec1);
- to_talitos_ptr_ext_or(ptr, DESC_PTR_LNKTBL_JUMP, is_sec1);
+ tbl_off * sizeof(struct talitos_ptr), aligned_len);
+ to_talitos_ptr_ext_or(ptr, DESC_PTR_LNKTBL_JUMP);
return sg_count;
}
@@ -875,9 +863,7 @@ struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
dma_addr_t iv_dma = 0;
gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
GFP_ATOMIC;
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
- int max_len = is_sec1 ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN;
+ int max_len = is_sec1() ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN;
if (cryptlen + authsize > max_len) {
dev_err(dev, "length exceeds h/w max limit\n");
@@ -918,7 +904,7 @@ struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
*/
alloc_len = sizeof(struct talitos_edesc);
if (src_nents || dst_nents || !encrypt) {
- if (is_sec1)
+ if (is_sec1())
dma_len = (src_nents ? src_len : 0) +
(dst_nents ? dst_len : 0) + authsize;
else
@@ -1094,14 +1080,13 @@ static int talitos_probe_irq(struct platform_device *ofdev)
struct device_node *np = ofdev->dev.of_node;
struct talitos_private *priv = dev_get_drvdata(dev);
int err;
- bool is_sec1 = has_ftr_sec1(priv);
priv->irq[0] = irq_of_parse_and_map(np, 0);
if (!priv->irq[0]) {
dev_err(dev, "failed to map irq\n");
return -EINVAL;
}
- if (is_sec1) {
+ if (is_sec1()) {
err = request_irq(priv->irq[0], talitos1_interrupt_4ch, 0,
dev_driver_string(dev), dev);
goto primary_out;
@@ -1196,12 +1181,10 @@ static int talitos_probe(struct platform_device *ofdev)
TALITOS_FTR_SHA224_HWINIT |
TALITOS_FTR_HMAC_OK;
- if (of_device_is_compatible(np, "fsl,sec1.0")) {
- priv->features |= TALITOS_FTR_SEC1;
+ if (of_device_is_compatible(np, "fsl,sec1.0"))
talitos_init_branch(true);
- } else {
+ else
talitos_init_branch(false);
- }
if (of_device_is_compatible(np, "fsl,sec1.2")) {
priv->reg_deu = priv->reg + TALITOS12_DEU;
@@ -1232,7 +1215,7 @@ static int talitos_probe(struct platform_device *ofdev)
if (err)
goto err_out;
- if (has_ftr_sec1(priv)) {
+ if (is_sec1()) {
if (priv->num_channels == 1)
tasklet_init(&priv->done_task[0], talitos1_done_ch0,
(unsigned long)dev);
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index b0d176c7dab2..9bbdd409da5a 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -223,7 +223,6 @@ struct talitos_crypto_alg {
#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
#define TALITOS_FTR_SHA224_HWINIT 0x00000004
#define TALITOS_FTR_HMAC_OK 0x00000008
-#define TALITOS_FTR_SEC1 0x00000010
#if defined(CONFIG_CRYPTO_DEV_TALITOS1) && defined(CONFIG_CRYPTO_DEV_TALITOS2)
DECLARE_STATIC_KEY_FALSE(talitos_is_sec1);
@@ -252,20 +251,6 @@ static inline void talitos_init_branch(bool sec1)
#endif
-/*
- * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
- * defined, we check the features which are set according to the device tree.
- * Otherwise, we answer true or false directly
- */
-static inline bool has_ftr_sec1(struct talitos_private *priv)
-{
- if (IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1) &&
- IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS2))
- return priv->features & TALITOS_FTR_SEC1;
-
- return IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1);
-}
-
/*
* TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
*/
@@ -504,10 +489,10 @@ static inline bool has_ftr_sec1(struct talitos_private *priv)
#define DESC_PTR_LNKTBL_NEXT 0x01
static inline void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
- unsigned int len, bool is_sec1)
+ unsigned int len)
{
ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
- if (is_sec1) {
+ if (is_sec1()) {
ptr->len1 = cpu_to_be16(len);
} else {
ptr->len = cpu_to_be16(len);
@@ -516,10 +501,10 @@ static inline void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
}
static inline void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
- struct talitos_ptr *src_ptr, bool is_sec1)
+ struct talitos_ptr *src_ptr)
{
dst_ptr->ptr = src_ptr->ptr;
- if (is_sec1) {
+ if (is_sec1()) {
dst_ptr->len1 = src_ptr->len1;
} else {
dst_ptr->len = src_ptr->len;
@@ -527,26 +512,23 @@ static inline void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
}
}
-static inline unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
- bool is_sec1)
+static inline unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr)
{
- if (is_sec1)
+ if (is_sec1())
return be16_to_cpu(ptr->len1);
else
return be16_to_cpu(ptr->len);
}
-static inline void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
- bool is_sec1)
+static inline void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val)
{
- if (!is_sec1)
+ if (!is_sec1())
ptr->j_extent = val;
}
-static inline void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val,
- bool is_sec1)
+static inline void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val)
{
- if (!is_sec1)
+ if (!is_sec1())
ptr->j_extent |= val;
}
@@ -559,10 +541,8 @@ static void __map_single_talitos_ptr(struct device *dev,
unsigned long attrs)
{
dma_addr_t dma_addr = dma_map_single_attrs(dev, data, len, dir, attrs);
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
- to_talitos_ptr(ptr, dma_addr, len, is_sec1);
+ to_talitos_ptr(ptr, dma_addr, len);
}
static inline void map_single_talitos_ptr(struct device *dev,
@@ -589,11 +569,8 @@ static inline void unmap_single_talitos_ptr(struct device *dev,
struct talitos_ptr *ptr,
enum dma_data_direction dir)
{
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
-
- dma_unmap_single(dev, be32_to_cpu(ptr->ptr),
- from_talitos_ptr_len(ptr, is_sec1), dir);
+ dma_unmap_single(dev, be32_to_cpu(ptr->ptr), from_talitos_ptr_len(ptr),
+ dir);
}
int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
--
2.54.0
^ permalink raw reply related
* [PATCH v2 16/19] crypto: talitos - Introduce is_sec1() helper with static key support
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
In preparation for per-SEC-version code paths, introduce an is_sec1()
inline helper that abstracts the SEC version check behind a static key.
The goal is to remove all bool is_sec1 parameters from the call chain via
the is_sec1() helper.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 10 +++++++++-
drivers/crypto/talitos/talitos.h | 28 ++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index ff938cc4e837..c93e3b551f6d 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -1196,8 +1196,12 @@ static int talitos_probe(struct platform_device *ofdev)
TALITOS_FTR_SHA224_HWINIT |
TALITOS_FTR_HMAC_OK;
- if (of_device_is_compatible(np, "fsl,sec1.0"))
+ if (of_device_is_compatible(np, "fsl,sec1.0")) {
priv->features |= TALITOS_FTR_SEC1;
+ talitos_init_branch(true);
+ } else {
+ talitos_init_branch(false);
+ }
if (of_device_is_compatible(np, "fsl,sec1.2")) {
priv->reg_deu = priv->reg + TALITOS12_DEU;
@@ -1317,6 +1321,10 @@ static int talitos_probe(struct platform_device *ofdev)
return err;
}
+#if defined(CONFIG_CRYPTO_DEV_TALITOS1) && defined(CONFIG_CRYPTO_DEV_TALITOS2)
+DEFINE_STATIC_KEY_FALSE(talitos_is_sec1);
+#endif
+
static const struct of_device_id talitos_match[] = {
#ifdef CONFIG_CRYPTO_DEV_TALITOS1
{
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 3cbce0be705d..b0d176c7dab2 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -14,6 +14,7 @@
#include <linux/dma-mapping.h>
#include <linux/hw_random.h>
#include <linux/interrupt.h>
+#include <linux/jump_label.h>
#include <linux/scatterlist.h>
#include <linux/types.h>
@@ -224,6 +225,33 @@ struct talitos_crypto_alg {
#define TALITOS_FTR_HMAC_OK 0x00000008
#define TALITOS_FTR_SEC1 0x00000010
+#if defined(CONFIG_CRYPTO_DEV_TALITOS1) && defined(CONFIG_CRYPTO_DEV_TALITOS2)
+DECLARE_STATIC_KEY_FALSE(talitos_is_sec1);
+
+static __always_inline bool is_sec1(void)
+{
+ return static_branch_unlikely(&talitos_is_sec1);
+}
+
+static inline void talitos_init_branch(bool sec1)
+{
+ if (sec1)
+ static_branch_enable(&talitos_is_sec1);
+}
+
+#else
+
+static __always_inline bool is_sec1(void)
+{
+ return IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1);
+}
+
+static inline void talitos_init_branch(bool sec1)
+{
+}
+
+#endif
+
/*
* If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
* defined, we check the features which are set according to the device tree.
--
2.54.0
^ permalink raw reply related
* [PATCH v2 15/19] crypto: talitos - Remove alg settings in talitos_register_common()
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Algorithm properties are now set at compile time for those who are not
dependent on runtime features.
Remove now-unused function and struct member.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 23 -----------------------
drivers/crypto/talitos/talitos.h | 1 -
2 files changed, 24 deletions(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 52ff5ef46fb6..ff938cc4e837 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -1040,23 +1040,6 @@ static void talitos_remove(struct platform_device *ofdev)
tasklet_kill(&priv->done_task[1]);
}
-static void talitos_alg_set_common(struct talitos_private *priv,
- struct crypto_alg *alg, u32 custom_priority,
- u32 type)
-{
- alg->cra_module = THIS_MODULE;
- if (custom_priority)
- alg->cra_priority = custom_priority;
- else
- alg->cra_priority = TALITOS_CRA_PRIORITY;
- if (has_ftr_sec1(priv) && type != CRYPTO_ALG_TYPE_AHASH)
- alg->cra_alignmask = 3;
- else
- alg->cra_alignmask = 0;
- alg->cra_ctxsize = sizeof(struct talitos_ctx);
- alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
-}
-
int talitos_register_common(struct device *dev,
struct talitos_alg_template *template)
{
@@ -1075,20 +1058,14 @@ int talitos_register_common(struct device *dev,
switch (t_alg->algt.type) {
case CRYPTO_ALG_TYPE_AHASH:
alg = &t_alg->algt.alg.hash.halg.base;
- talitos_alg_set_common(priv, alg, t_alg->algt.priority,
- t_alg->algt.type);
ret = crypto_register_ahash(&t_alg->algt.alg.hash);
break;
case CRYPTO_ALG_TYPE_SKCIPHER:
alg = &t_alg->algt.alg.skcipher.base;
- talitos_alg_set_common(priv, alg, t_alg->algt.priority,
- t_alg->algt.type);
ret = crypto_register_skcipher(&t_alg->algt.alg.skcipher);
break;
case CRYPTO_ALG_TYPE_AEAD:
alg = &t_alg->algt.alg.aead.base;
- talitos_alg_set_common(priv, alg, t_alg->algt.priority,
- t_alg->algt.type);
ret = crypto_register_aead(&t_alg->algt.alg.aead);
break;
default:
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index e36a2609d87d..3cbce0be705d 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -203,7 +203,6 @@ struct talitos_ctx {
struct talitos_alg_template {
u32 type;
- u32 priority;
union {
struct skcipher_alg skcipher;
struct ahash_alg hash;
--
2.54.0
^ permalink raw reply related
* [PATCH v2 11/19] crypto: talitos/aead - Convert to {init,exit}_tfm type-specific API
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Since commit 6eed1e3552fc0 ("crypto: api - Mark cra_init/cra_exit as
deprecated"), both cra_{init,exit} are deprecated.
Use {init,exit}_tfm instead.
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-aead.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos/talitos-aead.c
index ced314a645db..5537f2b6317f 100644
--- a/drivers/crypto/talitos/talitos-aead.c
+++ b/drivers/crypto/talitos/talitos-aead.c
@@ -400,6 +400,11 @@ static int talitos_cra_init_aead(struct crypto_aead *tfm)
return talitos_init_common(ctx, talitos_alg);
}
+static void talitos_cra_exit_aead(struct crypto_aead *tfm)
+{
+ talitos_cra_exit(crypto_aead_tfm(tfm));
+}
+
static struct talitos_alg_template aead_driver_algs[] = {
{ .type = CRYPTO_ALG_TYPE_AEAD,
.alg.aead = {
@@ -875,11 +880,11 @@ int talitos_register_aead(struct device *dev)
aead_alg = &aead_driver_algs[i].alg.aead;
alg = &aead_alg->base;
- alg->cra_exit = talitos_cra_exit;
if (has_ftr_sec1(priv))
alg->cra_alignmask = 3;
aead_alg->init = talitos_cra_init_aead;
+ aead_alg->exit = talitos_cra_exit_aead;
aead_alg->setkey = aead_alg->setkey ?: aead_setkey;
aead_alg->encrypt = aead_encrypt;
aead_alg->decrypt = aead_decrypt;
--
2.54.0
^ permalink raw reply related
* [PATCH v2 13/19] crypto: talitos/skcipher - Use macro for algorithm definitions
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Replace the repetitive struct initializer entries with preprocessor
macros.
The fallback setkey assignment (skcipher_alg->setkey ?: skcipher_setkey)
is no longer needed because each macro specifies the correct setkey
handler directly.
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-skcipher.c | 212 ++++++++++++------------------
1 file changed, 82 insertions(+), 130 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/talitos/talitos-skcipher.c
index 4c03573efb0a..b12191243aae 100644
--- a/drivers/crypto/talitos/talitos-skcipher.c
+++ b/drivers/crypto/talitos/talitos-skcipher.c
@@ -237,131 +237,89 @@ static void talitos_cra_exit_skcipher(struct crypto_skcipher *tfm)
talitos_cra_exit(crypto_skcipher_tfm(tfm));
}
+#define TALITOS_SKCIPHER_ALG_COMMON(name, blk_sz, iv_sz, min_ksz, max_ksz, \
+ set_key, desc_template) \
+ { \
+ .type = CRYPTO_ALG_TYPE_SKCIPHER, \
+ .alg.skcipher = { \
+ .base.cra_name = name, \
+ .base.cra_driver_name = name"-talitos", \
+ .base.cra_blocksize = blk_sz, \
+ .base.cra_flags = CRYPTO_ALG_ASYNC | \
+ CRYPTO_ALG_ALLOCATES_MEMORY | \
+ CRYPTO_ALG_KERN_DRIVER_ONLY, \
+ .base.cra_priority = TALITOS_CRA_PRIORITY, \
+ .base.cra_ctxsize = sizeof(struct talitos_ctx), \
+ .base.cra_module = THIS_MODULE, \
+ .min_keysize = min_ksz, \
+ .max_keysize = max_ksz, \
+ .ivsize = iv_sz, \
+ .setkey = set_key, \
+ .init = talitos_cra_init_skcipher, \
+ .exit = talitos_cra_exit_skcipher, \
+ .encrypt = skcipher_encrypt, \
+ .decrypt = skcipher_decrypt, \
+ }, \
+ .desc_hdr_template = desc_template, \
+ }
+
+#define TALITOS_SKCIPHER_ALG_AES(name, blk_sz, iv_sz, desc_template) \
+ TALITOS_SKCIPHER_ALG_COMMON(name, blk_sz, iv_sz, AES_MIN_KEY_SIZE, \
+ AES_MAX_KEY_SIZE, skcipher_aes_setkey, \
+ desc_template)
+
+#define TALITOS_SKCIPHER_ALG_DES(name, blk_sz, iv_sz, desc_template) \
+ TALITOS_SKCIPHER_ALG_COMMON(name, blk_sz, iv_sz, DES_KEY_SIZE, \
+ DES_KEY_SIZE, skcipher_des_setkey, \
+ desc_template)
+
+#define TALITOS_SKCIPHER_ALG_DES3(name, blk_sz, iv_sz, desc_template) \
+ TALITOS_SKCIPHER_ALG_COMMON(name, blk_sz, iv_sz, DES3_EDE_KEY_SIZE, \
+ DES3_EDE_KEY_SIZE, skcipher_des3_setkey, \
+ desc_template)
+
static struct talitos_alg_template skcipher_driver_algs[] = {
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(aes)",
- .base.cra_driver_name = "ecb-aes-talitos",
- .base.cra_blocksize = AES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(aes)",
- .base.cra_driver_name = "cbc-aes-talitos",
- .base.cra_blocksize = AES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ctr(aes)",
- .base.cra_driver_name = "ctr-aes-talitos",
- .base.cra_blocksize = 1,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_AESU_CTR_NONSNOOP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CTR,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ctr(aes)",
- .base.cra_driver_name = "ctr-aes-talitos",
- .base.cra_blocksize = 1,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CTR,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(des)",
- .base.cra_driver_name = "ecb-des-talitos",
- .base.cra_blocksize = DES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES_KEY_SIZE,
- .max_keysize = DES_KEY_SIZE,
- .setkey = skcipher_des_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(des)",
- .base.cra_driver_name = "cbc-des-talitos",
- .base.cra_blocksize = DES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES_KEY_SIZE,
- .max_keysize = DES_KEY_SIZE,
- .ivsize = DES_BLOCK_SIZE,
- .setkey = skcipher_des_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(des3_ede)",
- .base.cra_driver_name = "ecb-3des-talitos",
- .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES3_EDE_KEY_SIZE,
- .max_keysize = DES3_EDE_KEY_SIZE,
- .setkey = skcipher_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_3DES,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(des3_ede)",
- .base.cra_driver_name = "cbc-3des-talitos",
- .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES3_EDE_KEY_SIZE,
- .max_keysize = DES3_EDE_KEY_SIZE,
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .setkey = skcipher_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES,
- },
+ /* AES */
+
+ TALITOS_SKCIPHER_ALG_AES("ecb(aes)", AES_BLOCK_SIZE, 0,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU),
+
+ TALITOS_SKCIPHER_ALG_AES("cbc(aes)", AES_BLOCK_SIZE, AES_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC),
+
+ TALITOS_SKCIPHER_ALG_AES("ctr(aes)", 1, AES_BLOCK_SIZE,
+ DESC_HDR_TYPE_AESU_CTR_NONSNOOP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CTR),
+
+ TALITOS_SKCIPHER_ALG_AES("ctr(aes)", 1, AES_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CTR),
+ /* DES */
+
+ TALITOS_SKCIPHER_ALG_DES("ecb(des)", DES_BLOCK_SIZE, 0,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU),
+
+ TALITOS_SKCIPHER_ALG_DES("cbc(des)", DES_BLOCK_SIZE, DES_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC),
+ /* DES3 */
+
+ TALITOS_SKCIPHER_ALG_DES3("ecb(des3_ede)", DES3_EDE_BLOCK_SIZE, 0,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_3DES),
+
+ TALITOS_SKCIPHER_ALG_DES3(
+ "cbc(des3_ede)", DES3_EDE_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES),
};
int talitos_register_skcipher(struct device *dev)
@@ -383,12 +341,6 @@ int talitos_register_skcipher(struct device *dev)
if (has_ftr_sec1(priv))
alg->cra_alignmask = 3;
- skcipher_alg->init = talitos_cra_init_skcipher;
- skcipher_alg->exit = talitos_cra_exit_skcipher;
- skcipher_alg->setkey = skcipher_alg->setkey ?: skcipher_setkey;
- skcipher_alg->encrypt = skcipher_encrypt;
- skcipher_alg->decrypt = skcipher_decrypt;
-
if (!strcmp(alg->cra_name, "ctr(aes)") && !has_ftr_sec1(priv) &&
DESC_TYPE(skcipher_driver_algs[i].desc_hdr_template) !=
DESC_TYPE(DESC_HDR_TYPE_AESU_CTR_NONSNOOP)) {
--
2.54.0
^ permalink raw reply related
* [PATCH v2 14/19] crypto: talitos/aead - Use macro for algorithm definitions
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Replace the repetitive struct initializer entries with preprocessor
macros.
The fallback setkey assignment (aead_alg->setkey ?: aead_setkey) is
replaced by specifying the correct setkey handler directly in each macro
invocation.
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-aead.c | 679 +++++++++++-----------------------
1 file changed, 218 insertions(+), 461 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos/talitos-aead.c
index 5537f2b6317f..cd1b8e6d371b 100644
--- a/drivers/crypto/talitos/talitos-aead.c
+++ b/drivers/crypto/talitos/talitos-aead.c
@@ -405,463 +405,225 @@ static void talitos_cra_exit_aead(struct crypto_aead *tfm)
talitos_cra_exit(crypto_aead_tfm(tfm));
}
+#define TALITOS_AEAD_ALG_COMMON(name, name_prefix, set_key, block_size, \
+ max_auth_size, template, priority) \
+ { \
+ .type = CRYPTO_ALG_TYPE_AEAD, \
+ .alg.aead = { \
+ .base = { \
+ .cra_name = name, \
+ .cra_driver_name = name"-talitos"name_prefix, \
+ .cra_blocksize = block_size, \
+ .cra_flags = CRYPTO_ALG_ASYNC | \
+ CRYPTO_ALG_ALLOCATES_MEMORY | \
+ CRYPTO_ALG_KERN_DRIVER_ONLY, \
+ .cra_priority = (priority), \
+ .cra_ctxsize = sizeof(struct talitos_ctx), \
+ .cra_module = THIS_MODULE, \
+ }, \
+ .ivsize = block_size, \
+ .maxauthsize = max_auth_size, \
+ .setkey = set_key, \
+ .init = talitos_cra_init_aead, \
+ .exit = talitos_cra_exit_aead, \
+ .encrypt = aead_encrypt, \
+ .decrypt = aead_decrypt, \
+ }, \
+ .desc_hdr_template = template, \
+ }
+
+#define TALITOS_AEAD_ALG(name, set_key, block_size, max_auth_size, template) \
+ TALITOS_AEAD_ALG_COMMON(name, "", set_key, block_size, max_auth_size, \
+ template, TALITOS_CRA_PRIORITY)
+
+#define TALITOS_AEAD_ALG_HSNA(name, set_key, block_size, max_auth_size, \
+ template) \
+ TALITOS_AEAD_ALG_COMMON(name, "-hsna", set_key, block_size, \
+ max_auth_size, template, \
+ TALITOS_CRA_PRIORITY_AEAD_HSNA)
+
static struct talitos_alg_template aead_driver_algs[] = {
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha384),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha384-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA384_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha384),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha384-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA384_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha512),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha512-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA512_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha512),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha512-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA512_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(aes))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(aes))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
+ /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
+
+ /* sha1 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha1),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, SHA1_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha1),cbc(aes))", aead_setkey, AES_BLOCK_SIZE,
+ SHA1_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC),
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha1),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA1_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha1),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA1_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC),
+
+ /* sha224 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha224),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, SHA224_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha224),cbc(aes))", aead_setkey, AES_BLOCK_SIZE,
+ SHA224_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC),
+
+ TALITOS_AEAD_ALG(
+ "authenc(hmac(sha224),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA224_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha224),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA224_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC),
+
+ /* sha256 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha256),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, SHA256_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha256),cbc(aes))", aead_setkey, AES_BLOCK_SIZE,
+ SHA256_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC),
+
+ TALITOS_AEAD_ALG(
+ "authenc(hmac(sha256),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA256_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha256),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA256_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC),
+
+ /* sha384 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha384),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, SHA384_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA384_HMAC),
+
+ TALITOS_AEAD_ALG(
+ "authenc(hmac(sha384),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA384_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUB | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA384_HMAC),
+
+ /* sha512 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha512),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, SHA512_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA512_HMAC),
+
+ TALITOS_AEAD_ALG(
+ "authenc(hmac(sha512),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA512_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUB | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA512_HMAC),
+
+ /* md5 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(md5),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, MD5_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(md5),cbc(aes))", aead_setkey, AES_BLOCK_SIZE,
+ MD5_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC),
+
+ TALITOS_AEAD_ALG(
+ "authenc(hmac(md5),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, MD5_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD | DESC_HDR_MODE1_MDEU_MD5_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(md5),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, MD5_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD | DESC_HDR_MODE1_MDEU_MD5_HMAC),
};
int talitos_register_aead(struct device *dev)
@@ -883,11 +645,6 @@ int talitos_register_aead(struct device *dev)
if (has_ftr_sec1(priv))
alg->cra_alignmask = 3;
- aead_alg->init = talitos_cra_init_aead;
- aead_alg->exit = talitos_cra_exit_aead;
- aead_alg->setkey = aead_alg->setkey ?: aead_setkey;
- aead_alg->encrypt = aead_encrypt;
- aead_alg->decrypt = aead_decrypt;
if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
!strncmp(alg->cra_name, "authenc(hmac(sha224)", 20)) {
continue;
--
2.54.0
^ permalink raw reply related
* [PATCH v2 12/19] crypto: talitos/hash - Use macro for algorithm definitions
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Replace the repetitive struct initializer entries with preprocessor
macros.
The HMAC setkey assignment, previously done by comparing the algorithm
name at runtime, is now handled by passing ahash_setkey directly through
the TALITOS_HMAC_HASH_ALG macro variant.
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-hash.c | 344 ++++++++++------------------------
1 file changed, 104 insertions(+), 240 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos/talitos-hash.c
index 60e7f278243e..f3bffb0fdd2e 100644
--- a/drivers/crypto/talitos/talitos-hash.c
+++ b/drivers/crypto/talitos/talitos-hash.c
@@ -550,235 +550,111 @@ static void talitos_cra_exit_ahash(struct crypto_ahash *tfm)
talitos_cra_exit(crypto_ahash_tfm(tfm));
}
-static struct talitos_alg_template hash_driver_algs[] = {
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = MD5_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "md5",
- .cra_driver_name = "md5-talitos",
- .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_MD5,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA1_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha1",
- .cra_driver_name = "sha1-talitos",
- .cra_blocksize = SHA1_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA1,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA224_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha224",
- .cra_driver_name = "sha224-talitos",
- .cra_blocksize = SHA224_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA224,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA256_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha256",
- .cra_driver_name = "sha256-talitos",
- .cra_blocksize = SHA256_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA256,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA384_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha384",
- .cra_driver_name = "sha384-talitos",
- .cra_blocksize = SHA384_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA384,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA512_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha512",
- .cra_driver_name = "sha512-talitos",
- .cra_blocksize = SHA512_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA512,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = MD5_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(md5)",
- .cra_driver_name = "hmac-md5-talitos",
- .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_MD5,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA1_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha1)",
- .cra_driver_name = "hmac-sha1-talitos",
- .cra_blocksize = SHA1_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA1,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA224_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha224)",
- .cra_driver_name = "hmac-sha224-talitos",
- .cra_blocksize = SHA224_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA224,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA256_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha256)",
- .cra_driver_name = "hmac-sha256-talitos",
- .cra_blocksize = SHA256_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA256,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA384_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha384)",
- .cra_driver_name = "hmac-sha384-talitos",
- .cra_blocksize = SHA384_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA384,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA512_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha512)",
- .cra_driver_name = "hmac-sha512-talitos",
- .cra_blocksize = SHA512_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA512,
+#define TALITOS_HASH_ALG_COMMON(name, digest_size, block_size, template, \
+ set_key) \
+ { \
+ .type = CRYPTO_ALG_TYPE_AHASH, \
+ .alg.hash = { \
+ .init_tfm = talitos_cra_init_ahash, \
+ .exit_tfm = talitos_cra_exit_ahash, \
+ .init = ahash_init, \
+ .update = ahash_update, \
+ .final = ahash_final, \
+ .finup = ahash_finup, \
+ .digest = ahash_digest, \
+ .setkey = set_key, \
+ .import = ahash_import, \
+ .export = ahash_export, \
+ .halg.digestsize = digest_size, \
+ .halg.statesize = sizeof(struct talitos_export_state), \
+ .halg.base = { \
+ .cra_name = name, \
+ .cra_driver_name = name"-talitos", \
+ .cra_blocksize = block_size, \
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx), \
+ .cra_flags = CRYPTO_ALG_ASYNC | \
+ CRYPTO_ALG_ALLOCATES_MEMORY | \
+ CRYPTO_ALG_KERN_DRIVER_ONLY | \
+ CRYPTO_AHASH_ALG_BLOCK_ONLY | \
+ CRYPTO_AHASH_ALG_FINAL_NONZERO, \
+ .cra_priority = TALITOS_CRA_PRIORITY, \
+ .cra_ctxsize = sizeof(struct talitos_ctx), \
+ .cra_module = THIS_MODULE, \
+ }, \
+ }, \
+ .desc_hdr_template = template, \
}
+
+#define TALITOS_HASH_ALG(name, digest_size, block_size, desc_hdr_template) \
+ TALITOS_HASH_ALG_COMMON(name, digest_size, block_size, \
+ desc_hdr_template, NULL)
+
+#define TALITOS_HMAC_HASH_ALG(name, digest_size, block_size, \
+ desc_hdr_template) \
+ TALITOS_HASH_ALG_COMMON("hmac(" name ")", digest_size, block_size, \
+ desc_hdr_template, ahash_setkey)
+
+static struct talitos_alg_template hash_driver_algs[] = {
+ TALITOS_HASH_ALG("md5", MD5_DIGEST_SIZE, MD5_HMAC_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA | DESC_HDR_MODE0_MDEU_MD5),
+
+ TALITOS_HASH_ALG("sha1", SHA1_DIGEST_SIZE, SHA1_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA1),
+
+ TALITOS_HASH_ALG("sha224", SHA224_DIGEST_SIZE, SHA224_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA224),
+
+ TALITOS_HASH_ALG("sha256", SHA256_DIGEST_SIZE, SHA256_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA256),
+
+ TALITOS_HASH_ALG("sha384", SHA384_DIGEST_SIZE, SHA384_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA384),
+
+ TALITOS_HASH_ALG("sha512", SHA512_DIGEST_SIZE, SHA512_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA512),
+
+ /* HMAC */
+
+ TALITOS_HMAC_HASH_ALG("md5", MD5_DIGEST_SIZE, MD5_HMAC_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_MD5),
+
+ TALITOS_HMAC_HASH_ALG("sha1", SHA1_DIGEST_SIZE, SHA1_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA1),
+
+ TALITOS_HMAC_HASH_ALG("sha224", SHA224_DIGEST_SIZE, SHA224_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA224),
+
+ TALITOS_HMAC_HASH_ALG("sha256", SHA256_DIGEST_SIZE, SHA256_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA256),
+
+ TALITOS_HMAC_HASH_ALG("sha384", SHA384_DIGEST_SIZE, SHA384_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA384),
+
+ TALITOS_HMAC_HASH_ALG("sha512", SHA512_DIGEST_SIZE, SHA512_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA512),
};
int talitos_register_hash(struct device *dev)
@@ -797,18 +673,6 @@ int talitos_register_hash(struct device *dev)
ahash_alg = &hash_driver_algs[i].alg.hash;
alg = &ahash_alg->halg.base;
- ahash_alg->init_tfm = talitos_cra_init_ahash;
- ahash_alg->exit_tfm = talitos_cra_exit_ahash;
- ahash_alg->init = ahash_init;
- ahash_alg->update = ahash_update;
- ahash_alg->final = ahash_final;
- ahash_alg->finup = ahash_finup;
- ahash_alg->digest = ahash_digest;
- if (!strncmp(alg->cra_name, "hmac", 4))
- ahash_alg->setkey = ahash_setkey;
- ahash_alg->import = ahash_import;
- ahash_alg->export = ahash_export;
-
if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
!strncmp(alg->cra_name, "hmac", 4)) {
/* not supported */
--
2.54.0
^ permalink raw reply related
* [PATCH v2 10/19] crypto: talitos/skcipher - Convert to {init,exit}_tfm type-specific API
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Since commit 6eed1e3552fc0 ("crypto: api - Mark cra_init/cra_exit as
deprecated"), both cra_{init,exit} are deprecated.
Use {init,exit}_tfm instead.
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-skcipher.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/talitos/talitos-skcipher.c
index f80373610aa4..4c03573efb0a 100644
--- a/drivers/crypto/talitos/talitos-skcipher.c
+++ b/drivers/crypto/talitos/talitos-skcipher.c
@@ -232,6 +232,11 @@ static int talitos_cra_init_skcipher(struct crypto_skcipher *tfm)
return talitos_init_common(ctx, talitos_alg);
}
+static void talitos_cra_exit_skcipher(struct crypto_skcipher *tfm)
+{
+ talitos_cra_exit(crypto_skcipher_tfm(tfm));
+}
+
static struct talitos_alg_template skcipher_driver_algs[] = {
{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
.alg.skcipher = {
@@ -375,11 +380,11 @@ int talitos_register_skcipher(struct device *dev)
skcipher_alg = &skcipher_driver_algs[i].alg.skcipher;
alg = &skcipher_alg->base;
- alg->cra_exit = talitos_cra_exit;
if (has_ftr_sec1(priv))
alg->cra_alignmask = 3;
skcipher_alg->init = talitos_cra_init_skcipher;
+ skcipher_alg->exit = talitos_cra_exit_skcipher;
skcipher_alg->setkey = skcipher_alg->setkey ?: skcipher_setkey;
skcipher_alg->encrypt = skcipher_encrypt;
skcipher_alg->decrypt = skcipher_decrypt;
--
2.54.0
^ permalink raw reply related
* [PATCH v2 09/19] crypto: talitos/hash - Convert to {init,exit}_tfm type-specific API
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Since commit 6eed1e3552fc0 ("crypto: api - Mark cra_init/cra_exit as
deprecated"), both cra_{init,exit} are deprecated.
Use {init,exit}_tfm instead.
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-hash.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos/talitos-hash.c
index 76be6b6c6fcc..60e7f278243e 100644
--- a/drivers/crypto/talitos/talitos-hash.c
+++ b/drivers/crypto/talitos/talitos-hash.c
@@ -530,13 +530,13 @@ static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
return 0;
}
-static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
+static int talitos_cra_init_ahash(struct crypto_ahash *tfm)
{
- struct crypto_alg *alg = tfm->__crt_alg;
+ struct ahash_alg *alg = crypto_ahash_alg(tfm);
struct talitos_crypto_alg *talitos_alg;
- struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- talitos_alg = container_of(__crypto_ahash_alg(alg),
+ talitos_alg = container_of(alg,
struct talitos_crypto_alg,
algt.alg.hash);
@@ -545,6 +545,11 @@ static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
return talitos_init_common(ctx, talitos_alg);
}
+static void talitos_cra_exit_ahash(struct crypto_ahash *tfm)
+{
+ talitos_cra_exit(crypto_ahash_tfm(tfm));
+}
+
static struct talitos_alg_template hash_driver_algs[] = {
{ .type = CRYPTO_ALG_TYPE_AHASH,
.alg.hash = {
@@ -792,8 +797,8 @@ int talitos_register_hash(struct device *dev)
ahash_alg = &hash_driver_algs[i].alg.hash;
alg = &ahash_alg->halg.base;
- alg->cra_init = talitos_cra_init_ahash;
- alg->cra_exit = talitos_cra_exit;
+ ahash_alg->init_tfm = talitos_cra_init_ahash;
+ ahash_alg->exit_tfm = talitos_cra_exit_ahash;
ahash_alg->init = ahash_init;
ahash_alg->update = ahash_update;
ahash_alg->final = ahash_final;
--
2.54.0
^ permalink raw reply related
* [PATCH v2 03/19] crypto: talitos - Add missing includes to driver header file
From: Paul Louvel @ 2026-06-11 7:35 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Add explicit includes for types used by the header file to make
it self-contained and fix implicit include dependencies.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 3 ---
drivers/crypto/talitos/talitos.h | 6 ++++++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 12fb61ee8066..58663edd4ad4 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -15,10 +15,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
#include <linux/crypto.h>
-#include <linux/hw_random.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index d4ff8d589f46..56e36a65ddcc 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -5,6 +5,12 @@
* Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
*/
+#include <linux/device.h>
+#include <linux/hw_random.h>
+#include <linux/interrupt.h>
+#include <linux/scatterlist.h>
+#include <linux/types.h>
+
#define TALITOS_TIMEOUT 100000
#define TALITOS1_MAX_DATA_LEN 32768
#define TALITOS2_MAX_DATA_LEN 65535
--
2.54.0
^ permalink raw reply related
* [PATCH v2 08/19] crypto: talitos/aead - Move into separate file
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Move the AEAD algorithm implementations from talitos.c into
a dedicated talitos-aead.c file.
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/Makefile | 2 +-
drivers/crypto/talitos/talitos-aead.c | 897 ++++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.c | 947 +---------------------------------
drivers/crypto/talitos/talitos.h | 3 +
4 files changed, 910 insertions(+), 939 deletions(-)
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
index d4f19f2f6375..9e80bb094507 100644
--- a/drivers/crypto/talitos/Makefile
+++ b/drivers/crypto/talitos/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
-talitos-y := talitos.o talitos-rng.o talitos-hash.o talitos-skcipher.o
+talitos-y := talitos.o talitos-rng.o talitos-hash.o talitos-skcipher.o talitos-aead.o
diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos/talitos-aead.c
new file mode 100644
index 000000000000..ced314a645db
--- /dev/null
+++ b/drivers/crypto/talitos/talitos-aead.c
@@ -0,0 +1,897 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <crypto/authenc.h>
+#include <crypto/internal/des.h>
+#include <crypto/internal/aead.h>
+#include <crypto/md5.h>
+#include <crypto/sha1.h>
+#include <crypto/sha2.h>
+
+#include "talitos.h"
+
+/*
+ * Defines a priority for doing AEAD with descriptors type
+ * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP
+ */
+#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
+
+static int aead_setkey(struct crypto_aead *authenc,
+ const u8 *key, unsigned int keylen)
+{
+ struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
+ struct device *dev = ctx->dev;
+ struct crypto_authenc_keys keys;
+
+ if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
+ goto badkey;
+
+ if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
+ goto badkey;
+
+ if (ctx->keylen)
+ dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
+
+ memcpy(ctx->key, keys.authkey, keys.authkeylen);
+ memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
+
+ ctx->keylen = keys.authkeylen + keys.enckeylen;
+ ctx->enckeylen = keys.enckeylen;
+ ctx->authkeylen = keys.authkeylen;
+ ctx->dma_key = dma_map_single(dev, ctx->key, ctx->keylen,
+ DMA_TO_DEVICE);
+
+ memzero_explicit(&keys, sizeof(keys));
+ return 0;
+
+badkey:
+ memzero_explicit(&keys, sizeof(keys));
+ return -EINVAL;
+}
+
+static int aead_des3_setkey(struct crypto_aead *authenc,
+ const u8 *key, unsigned int keylen)
+{
+ struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
+ struct device *dev = ctx->dev;
+ struct crypto_authenc_keys keys;
+ int err;
+
+ err = crypto_authenc_extractkeys(&keys, key, keylen);
+ if (unlikely(err))
+ goto out;
+
+ err = -EINVAL;
+ if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
+ goto out;
+
+ err = verify_aead_des3_key(authenc, keys.enckey, keys.enckeylen);
+ if (err)
+ goto out;
+
+ if (ctx->keylen)
+ dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
+
+ memcpy(ctx->key, keys.authkey, keys.authkeylen);
+ memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
+
+ ctx->keylen = keys.authkeylen + keys.enckeylen;
+ ctx->enckeylen = keys.enckeylen;
+ ctx->authkeylen = keys.authkeylen;
+ ctx->dma_key = dma_map_single(dev, ctx->key, ctx->keylen,
+ DMA_TO_DEVICE);
+
+out:
+ memzero_explicit(&keys, sizeof(keys));
+ return err;
+}
+
+static void ipsec_esp_unmap(struct device *dev,
+ struct talitos_edesc *edesc,
+ struct aead_request *areq, bool encrypt)
+{
+ struct crypto_aead *aead = crypto_aead_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_aead_ctx(aead);
+ unsigned int ivsize = crypto_aead_ivsize(aead);
+ unsigned int authsize = crypto_aead_authsize(aead);
+ unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
+ bool is_ipsec_esp = edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP;
+ struct talitos_ptr *civ_ptr = &edesc->desc.ptr[is_ipsec_esp ? 2 : 3];
+
+ if (is_ipsec_esp)
+ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6],
+ DMA_FROM_DEVICE);
+ unmap_single_talitos_ptr(dev, civ_ptr, DMA_TO_DEVICE);
+
+ talitos_sg_unmap(dev, edesc, areq->src, areq->dst,
+ cryptlen + authsize, areq->assoclen);
+
+ if (edesc->dma_len)
+ dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
+ DMA_BIDIRECTIONAL);
+
+ if (!is_ipsec_esp) {
+ unsigned int dst_nents = edesc->dst_nents ? : 1;
+
+ sg_pcopy_to_buffer(areq->dst, dst_nents, ctx->iv, ivsize,
+ areq->assoclen + cryptlen - ivsize);
+ }
+}
+
+/*
+ * ipsec_esp descriptor callbacks
+ */
+static void ipsec_esp_encrypt_done(struct device *dev,
+ struct talitos_desc *desc, void *context,
+ int err)
+{
+ struct aead_request *areq = context;
+ struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
+ unsigned int ivsize = crypto_aead_ivsize(authenc);
+ struct talitos_edesc *edesc;
+
+ edesc = container_of(desc, struct talitos_edesc, desc);
+
+ ipsec_esp_unmap(dev, edesc, areq, true);
+
+ dma_unmap_single(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
+
+ kfree(edesc);
+
+ aead_request_complete(areq, err);
+}
+
+static void ipsec_esp_decrypt_swauth_done(struct device *dev,
+ struct talitos_desc *desc,
+ void *context, int err)
+{
+ struct aead_request *req = context;
+ struct crypto_aead *authenc = crypto_aead_reqtfm(req);
+ unsigned int authsize = crypto_aead_authsize(authenc);
+ struct talitos_edesc *edesc;
+ char *oicv, *icv;
+
+ edesc = container_of(desc, struct talitos_edesc, desc);
+
+ ipsec_esp_unmap(dev, edesc, req, false);
+
+ if (!err) {
+ /* auth check */
+ oicv = edesc->buf + edesc->dma_len;
+ icv = oicv - authsize;
+
+ err = crypto_memneq(oicv, icv, authsize) ? -EBADMSG : 0;
+ }
+
+ kfree(edesc);
+
+ aead_request_complete(req, err);
+}
+
+static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
+ struct talitos_desc *desc,
+ void *context, int err)
+{
+ struct aead_request *req = context;
+ struct talitos_edesc *edesc;
+
+ edesc = container_of(desc, struct talitos_edesc, desc);
+
+ ipsec_esp_unmap(dev, edesc, req, false);
+
+ /* check ICV auth status */
+ if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
+ DESC_HDR_LO_ICCR1_PASS))
+ err = -EBADMSG;
+
+ kfree(edesc);
+
+ aead_request_complete(req, err);
+}
+
+/*
+ * fill in and submit ipsec_esp descriptor
+ */
+static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
+ bool encrypt,
+ void (*callback)(struct device *dev,
+ struct talitos_desc *desc,
+ void *context, int error))
+{
+ struct crypto_aead *aead = crypto_aead_reqtfm(areq);
+ unsigned int authsize = crypto_aead_authsize(aead);
+ struct talitos_ctx *ctx = crypto_aead_ctx(aead);
+ struct device *dev = ctx->dev;
+ struct talitos_desc *desc = &edesc->desc;
+ unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
+ unsigned int ivsize = crypto_aead_ivsize(aead);
+ int tbl_off = 0;
+ int sg_count, ret;
+ int elen = 0;
+ bool sync_needed = false;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+ bool is_ipsec_esp = desc->hdr & DESC_HDR_TYPE_IPSEC_ESP;
+ struct talitos_ptr *civ_ptr = &desc->ptr[is_ipsec_esp ? 2 : 3];
+ struct talitos_ptr *ckey_ptr = &desc->ptr[is_ipsec_esp ? 3 : 2];
+ dma_addr_t dma_icv = edesc->dma_link_tbl + edesc->dma_len - authsize;
+
+ /* hmac key */
+ to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen, is_sec1);
+
+ sg_count = edesc->src_nents ?: 1;
+ if (is_sec1 && sg_count > 1)
+ sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
+ areq->assoclen + cryptlen);
+ else
+ sg_count = dma_map_sg(dev, areq->src, sg_count,
+ (areq->src == areq->dst) ?
+ DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
+
+ /* hmac data */
+ ret = talitos_sg_map(dev, areq->src, areq->assoclen, edesc,
+ &desc->ptr[1], sg_count, 0, tbl_off);
+
+ if (ret > 1) {
+ tbl_off += ret;
+ sync_needed = true;
+ }
+
+ /* cipher iv */
+ to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize, is_sec1);
+
+ /* cipher key */
+ to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen,
+ ctx->enckeylen, is_sec1);
+
+ /*
+ * cipher in
+ * map and adjust cipher len to aead request cryptlen.
+ * extent is bytes of HMAC postpended to ciphertext,
+ * typically 12 for ipsec
+ */
+ if (is_ipsec_esp && (desc->hdr & DESC_HDR_MODE1_MDEU_CICV))
+ elen = authsize;
+
+ ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4],
+ sg_count, areq->assoclen, tbl_off, elen,
+ false, 1);
+
+ if (ret > 1) {
+ tbl_off += ret;
+ sync_needed = true;
+ }
+
+ /* cipher out */
+ if (areq->src != areq->dst) {
+ sg_count = edesc->dst_nents ? : 1;
+ if (!is_sec1 || sg_count == 1)
+ dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
+ }
+
+ if (is_ipsec_esp && encrypt)
+ elen = authsize;
+ else
+ elen = 0;
+ ret = talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, &desc->ptr[5],
+ sg_count, areq->assoclen, tbl_off, elen,
+ is_ipsec_esp && !encrypt, 1);
+ tbl_off += ret;
+
+ if (!encrypt && is_ipsec_esp) {
+ struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
+
+ /* Add an entry to the link table for ICV data */
+ to_talitos_ptr_ext_set(tbl_ptr - 1, 0, is_sec1);
+ to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET, is_sec1);
+
+ /* icv data follows link tables */
+ to_talitos_ptr(tbl_ptr, dma_icv, authsize, is_sec1);
+ to_talitos_ptr_ext_or(&desc->ptr[5], authsize, is_sec1);
+ sync_needed = true;
+ } else if (!encrypt) {
+ to_talitos_ptr(&desc->ptr[6], dma_icv, authsize, is_sec1);
+ sync_needed = true;
+ } else if (!is_ipsec_esp) {
+ talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6],
+ sg_count, areq->assoclen + cryptlen, tbl_off);
+ }
+
+ /* iv out */
+ if (is_ipsec_esp)
+ map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
+ DMA_FROM_DEVICE);
+
+ if (sync_needed)
+ dma_sync_single_for_device(dev, edesc->dma_link_tbl,
+ edesc->dma_len,
+ DMA_BIDIRECTIONAL);
+
+ ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
+ if (ret != -EINPROGRESS) {
+ ipsec_esp_unmap(dev, edesc, areq, encrypt);
+ kfree(edesc);
+ }
+ return ret;
+}
+
+static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
+ int icv_stashing, bool encrypt)
+{
+ struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
+ unsigned int authsize = crypto_aead_authsize(authenc);
+ struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
+ unsigned int ivsize = crypto_aead_ivsize(authenc);
+ unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
+
+ return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
+ iv, areq->assoclen, cryptlen,
+ authsize, ivsize, icv_stashing,
+ areq->base.flags, encrypt);
+}
+
+static int aead_encrypt(struct aead_request *req)
+{
+ struct crypto_aead *authenc = crypto_aead_reqtfm(req);
+ struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
+ struct talitos_edesc *edesc;
+
+ /* allocate extended descriptor */
+ edesc = aead_edesc_alloc(req, req->iv, 0, true);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+ /* set encrypt */
+ edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
+
+ return ipsec_esp(edesc, req, true, ipsec_esp_encrypt_done);
+}
+
+static int aead_decrypt(struct aead_request *req)
+{
+ struct crypto_aead *authenc = crypto_aead_reqtfm(req);
+ unsigned int authsize = crypto_aead_authsize(authenc);
+ struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
+ struct talitos_private *priv = dev_get_drvdata(ctx->dev);
+ struct talitos_edesc *edesc;
+ void *icvdata;
+
+ /* allocate extended descriptor */
+ edesc = aead_edesc_alloc(req, req->iv, 1, false);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+ if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) &&
+ (priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
+ ((!edesc->src_nents && !edesc->dst_nents) ||
+ priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
+
+ /* decrypt and check the ICV */
+ edesc->desc.hdr = ctx->desc_hdr_template |
+ DESC_HDR_DIR_INBOUND |
+ DESC_HDR_MODE1_MDEU_CICV;
+
+ /* reset integrity check result bits */
+
+ return ipsec_esp(edesc, req, false,
+ ipsec_esp_decrypt_hwauth_done);
+ }
+
+ /* Have to check the ICV with software */
+ edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
+
+ /* stash incoming ICV for later cmp with ICV generated by the h/w */
+ icvdata = edesc->buf + edesc->dma_len;
+
+ sg_pcopy_to_buffer(req->src, edesc->src_nents ? : 1, icvdata, authsize,
+ req->assoclen + req->cryptlen - authsize);
+
+ return ipsec_esp(edesc, req, false, ipsec_esp_decrypt_swauth_done);
+}
+
+static int talitos_cra_init_aead(struct crypto_aead *tfm)
+{
+ struct aead_alg *alg = crypto_aead_alg(tfm);
+ struct talitos_crypto_alg *talitos_alg;
+ struct talitos_ctx *ctx = crypto_aead_ctx(tfm);
+
+ talitos_alg = container_of(alg, struct talitos_crypto_alg,
+ algt.alg.aead);
+
+ return talitos_init_common(ctx, talitos_alg);
+}
+
+static struct talitos_alg_template aead_driver_algs[] = {
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha1),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha1-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA1_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha1),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha1-"
+ "cbc-aes-talitos-hsna",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA1_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha1),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha1-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA1_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha1),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha1-"
+ "cbc-3des-talitos-hsna",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA1_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha224),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha224-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA224_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha224),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha224-"
+ "cbc-aes-talitos-hsna",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA224_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha224),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha224-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA224_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha224),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha224-"
+ "cbc-3des-talitos-hsna",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA224_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha256),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha256-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA256_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha256),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha256-"
+ "cbc-aes-talitos-hsna",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA256_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha256),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha256-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA256_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha256),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha256-"
+ "cbc-3des-talitos-hsna",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA256_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha384),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha384-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA384_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha384),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha384-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA384_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha512),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha512-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA512_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha512),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha512-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA512_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(md5),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-md5-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = MD5_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(md5),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-md5-"
+ "cbc-aes-talitos-hsna",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = MD5_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-md5-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = MD5_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-md5-"
+ "cbc-3des-talitos-hsna",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = MD5_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC,
+ },
+};
+
+int talitos_register_aead(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ struct aead_alg *aead_alg;
+ struct crypto_alg *alg;
+ size_t i;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(aead_driver_algs); i++) {
+ if (!talitos_hw_supports(dev,
+ aead_driver_algs[i].desc_hdr_template))
+ continue;
+
+ aead_alg = &aead_driver_algs[i].alg.aead;
+ alg = &aead_alg->base;
+
+ alg->cra_exit = talitos_cra_exit;
+ if (has_ftr_sec1(priv))
+ alg->cra_alignmask = 3;
+
+ aead_alg->init = talitos_cra_init_aead;
+ aead_alg->setkey = aead_alg->setkey ?: aead_setkey;
+ aead_alg->encrypt = aead_encrypt;
+ aead_alg->decrypt = aead_decrypt;
+ if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
+ !strncmp(alg->cra_name, "authenc(hmac(sha224)", 20)) {
+ continue;
+ }
+
+ ret = talitos_register_common(dev, &aead_driver_algs[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 4b77253e04fa..52ff5ef46fb6 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -727,87 +727,6 @@ DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE, TALITOS2_ISR_CH_0_2_ERR,
DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
1)
-
-/*
- * crypto alg
- */
-#define TALITOS_CRA_PRIORITY 3000
-/*
- * Defines a priority for doing AEAD with descriptors type
- * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP
- */
-#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
-
-static int aead_setkey(struct crypto_aead *authenc,
- const u8 *key, unsigned int keylen)
-{
- struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
- struct device *dev = ctx->dev;
- struct crypto_authenc_keys keys;
-
- if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
- goto badkey;
-
- if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
- goto badkey;
-
- if (ctx->keylen)
- dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
-
- memcpy(ctx->key, keys.authkey, keys.authkeylen);
- memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
-
- ctx->keylen = keys.authkeylen + keys.enckeylen;
- ctx->enckeylen = keys.enckeylen;
- ctx->authkeylen = keys.authkeylen;
- ctx->dma_key = dma_map_single(dev, ctx->key, ctx->keylen,
- DMA_TO_DEVICE);
-
- memzero_explicit(&keys, sizeof(keys));
- return 0;
-
-badkey:
- memzero_explicit(&keys, sizeof(keys));
- return -EINVAL;
-}
-
-static int aead_des3_setkey(struct crypto_aead *authenc,
- const u8 *key, unsigned int keylen)
-{
- struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
- struct device *dev = ctx->dev;
- struct crypto_authenc_keys keys;
- int err;
-
- err = crypto_authenc_extractkeys(&keys, key, keylen);
- if (unlikely(err))
- goto out;
-
- err = -EINVAL;
- if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
- goto out;
-
- err = verify_aead_des3_key(authenc, keys.enckey, keys.enckeylen);
- if (err)
- goto out;
-
- if (ctx->keylen)
- dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
-
- memcpy(ctx->key, keys.authkey, keys.authkeylen);
- memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
-
- ctx->keylen = keys.authkeylen + keys.enckeylen;
- ctx->enckeylen = keys.enckeylen;
- ctx->authkeylen = keys.authkeylen;
- ctx->dma_key = dma_map_single(dev, ctx->key, ctx->keylen,
- DMA_TO_DEVICE);
-
-out:
- memzero_explicit(&keys, sizeof(keys));
- return err;
-}
-
void talitos_sg_unmap(struct device *dev,
struct talitos_edesc *edesc,
struct scatterlist *src,
@@ -836,109 +755,6 @@ void talitos_sg_unmap(struct device *dev,
}
}
-static void ipsec_esp_unmap(struct device *dev,
- struct talitos_edesc *edesc,
- struct aead_request *areq, bool encrypt)
-{
- struct crypto_aead *aead = crypto_aead_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_aead_ctx(aead);
- unsigned int ivsize = crypto_aead_ivsize(aead);
- unsigned int authsize = crypto_aead_authsize(aead);
- unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
- bool is_ipsec_esp = edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP;
- struct talitos_ptr *civ_ptr = &edesc->desc.ptr[is_ipsec_esp ? 2 : 3];
-
- if (is_ipsec_esp)
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6],
- DMA_FROM_DEVICE);
- unmap_single_talitos_ptr(dev, civ_ptr, DMA_TO_DEVICE);
-
- talitos_sg_unmap(dev, edesc, areq->src, areq->dst,
- cryptlen + authsize, areq->assoclen);
-
- if (edesc->dma_len)
- dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
- DMA_BIDIRECTIONAL);
-
- if (!is_ipsec_esp) {
- unsigned int dst_nents = edesc->dst_nents ? : 1;
-
- sg_pcopy_to_buffer(areq->dst, dst_nents, ctx->iv, ivsize,
- areq->assoclen + cryptlen - ivsize);
- }
-}
-
-/*
- * ipsec_esp descriptor callbacks
- */
-static void ipsec_esp_encrypt_done(struct device *dev,
- struct talitos_desc *desc, void *context,
- int err)
-{
- struct aead_request *areq = context;
- struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
- unsigned int ivsize = crypto_aead_ivsize(authenc);
- struct talitos_edesc *edesc;
-
- edesc = container_of(desc, struct talitos_edesc, desc);
-
- ipsec_esp_unmap(dev, edesc, areq, true);
-
- dma_unmap_single(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
-
- kfree(edesc);
-
- aead_request_complete(areq, err);
-}
-
-static void ipsec_esp_decrypt_swauth_done(struct device *dev,
- struct talitos_desc *desc,
- void *context, int err)
-{
- struct aead_request *req = context;
- struct crypto_aead *authenc = crypto_aead_reqtfm(req);
- unsigned int authsize = crypto_aead_authsize(authenc);
- struct talitos_edesc *edesc;
- char *oicv, *icv;
-
- edesc = container_of(desc, struct talitos_edesc, desc);
-
- ipsec_esp_unmap(dev, edesc, req, false);
-
- if (!err) {
- /* auth check */
- oicv = edesc->buf + edesc->dma_len;
- icv = oicv - authsize;
-
- err = crypto_memneq(oicv, icv, authsize) ? -EBADMSG : 0;
- }
-
- kfree(edesc);
-
- aead_request_complete(req, err);
-}
-
-static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
- struct talitos_desc *desc,
- void *context, int err)
-{
- struct aead_request *req = context;
- struct talitos_edesc *edesc;
-
- edesc = container_of(desc, struct talitos_edesc, desc);
-
- ipsec_esp_unmap(dev, edesc, req, false);
-
- /* check ICV auth status */
- if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
- DESC_HDR_LO_ICCR1_PASS))
- err = -EBADMSG;
-
- kfree(edesc);
-
- aead_request_complete(req, err);
-}
-
/*
* convert scatterlist to SEC h/w link table format
* stop at cryptlen bytes
@@ -1039,132 +855,6 @@ int talitos_sg_map(struct device *dev, struct scatterlist *src,
tbl_off, 0, false, 1);
}
-/*
- * fill in and submit ipsec_esp descriptor
- */
-static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
- bool encrypt,
- void (*callback)(struct device *dev,
- struct talitos_desc *desc,
- void *context, int error))
-{
- struct crypto_aead *aead = crypto_aead_reqtfm(areq);
- unsigned int authsize = crypto_aead_authsize(aead);
- struct talitos_ctx *ctx = crypto_aead_ctx(aead);
- struct device *dev = ctx->dev;
- struct talitos_desc *desc = &edesc->desc;
- unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
- unsigned int ivsize = crypto_aead_ivsize(aead);
- int tbl_off = 0;
- int sg_count, ret;
- int elen = 0;
- bool sync_needed = false;
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
- bool is_ipsec_esp = desc->hdr & DESC_HDR_TYPE_IPSEC_ESP;
- struct talitos_ptr *civ_ptr = &desc->ptr[is_ipsec_esp ? 2 : 3];
- struct talitos_ptr *ckey_ptr = &desc->ptr[is_ipsec_esp ? 3 : 2];
- dma_addr_t dma_icv = edesc->dma_link_tbl + edesc->dma_len - authsize;
-
- /* hmac key */
- to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen, is_sec1);
-
- sg_count = edesc->src_nents ?: 1;
- if (is_sec1 && sg_count > 1)
- sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
- areq->assoclen + cryptlen);
- else
- sg_count = dma_map_sg(dev, areq->src, sg_count,
- (areq->src == areq->dst) ?
- DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
-
- /* hmac data */
- ret = talitos_sg_map(dev, areq->src, areq->assoclen, edesc,
- &desc->ptr[1], sg_count, 0, tbl_off);
-
- if (ret > 1) {
- tbl_off += ret;
- sync_needed = true;
- }
-
- /* cipher iv */
- to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize, is_sec1);
-
- /* cipher key */
- to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen,
- ctx->enckeylen, is_sec1);
-
- /*
- * cipher in
- * map and adjust cipher len to aead request cryptlen.
- * extent is bytes of HMAC postpended to ciphertext,
- * typically 12 for ipsec
- */
- if (is_ipsec_esp && (desc->hdr & DESC_HDR_MODE1_MDEU_CICV))
- elen = authsize;
-
- ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4],
- sg_count, areq->assoclen, tbl_off, elen,
- false, 1);
-
- if (ret > 1) {
- tbl_off += ret;
- sync_needed = true;
- }
-
- /* cipher out */
- if (areq->src != areq->dst) {
- sg_count = edesc->dst_nents ? : 1;
- if (!is_sec1 || sg_count == 1)
- dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
- }
-
- if (is_ipsec_esp && encrypt)
- elen = authsize;
- else
- elen = 0;
- ret = talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, &desc->ptr[5],
- sg_count, areq->assoclen, tbl_off, elen,
- is_ipsec_esp && !encrypt, 1);
- tbl_off += ret;
-
- if (!encrypt && is_ipsec_esp) {
- struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
-
- /* Add an entry to the link table for ICV data */
- to_talitos_ptr_ext_set(tbl_ptr - 1, 0, is_sec1);
- to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET, is_sec1);
-
- /* icv data follows link tables */
- to_talitos_ptr(tbl_ptr, dma_icv, authsize, is_sec1);
- to_talitos_ptr_ext_or(&desc->ptr[5], authsize, is_sec1);
- sync_needed = true;
- } else if (!encrypt) {
- to_talitos_ptr(&desc->ptr[6], dma_icv, authsize, is_sec1);
- sync_needed = true;
- } else if (!is_ipsec_esp) {
- talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6],
- sg_count, areq->assoclen + cryptlen, tbl_off);
- }
-
- /* iv out */
- if (is_ipsec_esp)
- map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
- DMA_FROM_DEVICE);
-
- if (sync_needed)
- dma_sync_single_for_device(dev, edesc->dma_link_tbl,
- edesc->dma_len,
- DMA_BIDIRECTIONAL);
-
- ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
- if (ret != -EINPROGRESS) {
- ipsec_esp_unmap(dev, edesc, areq, encrypt);
- kfree(edesc);
- }
- return ret;
-}
-
/*
* allocate and map the extended descriptor
*/
@@ -1263,540 +953,6 @@ struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
return edesc;
}
-static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
- int icv_stashing, bool encrypt)
-{
- struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
- unsigned int authsize = crypto_aead_authsize(authenc);
- struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
- unsigned int ivsize = crypto_aead_ivsize(authenc);
- unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
-
- return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
- iv, areq->assoclen, cryptlen,
- authsize, ivsize, icv_stashing,
- areq->base.flags, encrypt);
-}
-
-static int aead_encrypt(struct aead_request *req)
-{
- struct crypto_aead *authenc = crypto_aead_reqtfm(req);
- struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
- struct talitos_edesc *edesc;
-
- /* allocate extended descriptor */
- edesc = aead_edesc_alloc(req, req->iv, 0, true);
- if (IS_ERR(edesc))
- return PTR_ERR(edesc);
-
- /* set encrypt */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
-
- return ipsec_esp(edesc, req, true, ipsec_esp_encrypt_done);
-}
-
-static int aead_decrypt(struct aead_request *req)
-{
- struct crypto_aead *authenc = crypto_aead_reqtfm(req);
- unsigned int authsize = crypto_aead_authsize(authenc);
- struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
- struct talitos_private *priv = dev_get_drvdata(ctx->dev);
- struct talitos_edesc *edesc;
- void *icvdata;
-
- /* allocate extended descriptor */
- edesc = aead_edesc_alloc(req, req->iv, 1, false);
- if (IS_ERR(edesc))
- return PTR_ERR(edesc);
-
- if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) &&
- (priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
- ((!edesc->src_nents && !edesc->dst_nents) ||
- priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
-
- /* decrypt and check the ICV */
- edesc->desc.hdr = ctx->desc_hdr_template |
- DESC_HDR_DIR_INBOUND |
- DESC_HDR_MODE1_MDEU_CICV;
-
- /* reset integrity check result bits */
-
- return ipsec_esp(edesc, req, false,
- ipsec_esp_decrypt_hwauth_done);
- }
-
- /* Have to check the ICV with software */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
-
- /* stash incoming ICV for later cmp with ICV generated by the h/w */
- icvdata = edesc->buf + edesc->dma_len;
-
- sg_pcopy_to_buffer(req->src, edesc->src_nents ? : 1, icvdata, authsize,
- req->assoclen + req->cryptlen - authsize);
-
- return ipsec_esp(edesc, req, false, ipsec_esp_decrypt_swauth_done);
-}
-
-static struct talitos_alg_template driver_algs[] = {
- /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha384),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha384-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA384_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha384),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha384-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA384_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha512),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha512-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA512_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha512),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha512-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA512_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(aes))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(aes))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
-};
-
int talitos_init_common(struct talitos_ctx *ctx,
struct talitos_crypto_alg *talitos_alg)
{
@@ -1819,18 +975,6 @@ int talitos_init_common(struct talitos_ctx *ctx,
return 0;
}
-static int talitos_cra_init_aead(struct crypto_aead *tfm)
-{
- struct aead_alg *alg = crypto_aead_alg(tfm);
- struct talitos_crypto_alg *talitos_alg;
- struct talitos_ctx *ctx = crypto_aead_ctx(tfm);
-
- talitos_alg = container_of(alg, struct talitos_crypto_alg,
- algt.alg.aead);
-
- return talitos_init_common(ctx, talitos_alg);
-}
-
void talitos_cra_exit(struct crypto_tfm *tfm)
{
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
@@ -1941,6 +1085,12 @@ int talitos_register_common(struct device *dev,
t_alg->algt.type);
ret = crypto_register_skcipher(&t_alg->algt.alg.skcipher);
break;
+ case CRYPTO_ALG_TYPE_AEAD:
+ alg = &t_alg->algt.alg.aead.base;
+ talitos_alg_set_common(priv, alg, t_alg->algt.priority,
+ t_alg->algt.type);
+ ret = crypto_register_aead(&t_alg->algt.alg.aead);
+ break;
default:
dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
devm_kfree(dev, t_alg);
@@ -1961,59 +1111,6 @@ int talitos_register_common(struct device *dev,
return 0;
}
-static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
- struct talitos_alg_template
- *template)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
- struct talitos_crypto_alg *t_alg;
- struct crypto_alg *alg;
-
- t_alg = devm_kzalloc(dev, sizeof(struct talitos_crypto_alg),
- GFP_KERNEL);
- if (!t_alg)
- return ERR_PTR(-ENOMEM);
-
- t_alg->algt = *template;
-
- switch (t_alg->algt.type) {
- case CRYPTO_ALG_TYPE_AEAD:
- alg = &t_alg->algt.alg.aead.base;
- alg->cra_exit = talitos_cra_exit;
- t_alg->algt.alg.aead.init = talitos_cra_init_aead;
- t_alg->algt.alg.aead.setkey = t_alg->algt.alg.aead.setkey ?:
- aead_setkey;
- t_alg->algt.alg.aead.encrypt = aead_encrypt;
- t_alg->algt.alg.aead.decrypt = aead_decrypt;
- if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
- !strncmp(alg->cra_name, "authenc(hmac(sha224)", 20)) {
- devm_kfree(dev, t_alg);
- return ERR_PTR(-ENOTSUPP);
- }
- break;
- default:
- dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
- devm_kfree(dev, t_alg);
- return ERR_PTR(-EINVAL);
- }
-
- alg->cra_module = THIS_MODULE;
- if (t_alg->algt.priority)
- alg->cra_priority = t_alg->algt.priority;
- else
- alg->cra_priority = TALITOS_CRA_PRIORITY;
- if (has_ftr_sec1(priv) && t_alg->algt.type != CRYPTO_ALG_TYPE_AHASH)
- alg->cra_alignmask = 3;
- else
- alg->cra_alignmask = 0;
- alg->cra_ctxsize = sizeof(struct talitos_ctx);
- alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
-
- t_alg->dev = dev;
-
- return t_alg;
-}
-
static int talitos_probe_irq(struct platform_device *ofdev)
{
struct device *dev = &ofdev->dev;
@@ -2227,36 +1324,10 @@ static int talitos_probe(struct platform_device *ofdev)
if (err)
goto err_out;
- /* register crypto algorithms the device supports */
- for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
- if (talitos_hw_supports(dev,
- driver_algs[i].desc_hdr_template)) {
- struct talitos_crypto_alg *t_alg;
- struct crypto_alg *alg = NULL;
-
- t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
- if (IS_ERR(t_alg)) {
- err = PTR_ERR(t_alg);
- if (err == -ENOTSUPP)
- continue;
- goto err_out;
- }
+ err = talitos_register_aead(dev);
+ if (err)
+ goto err_out;
- switch (t_alg->algt.type) {
- case CRYPTO_ALG_TYPE_AEAD:
- err = crypto_register_aead(
- &t_alg->algt.alg.aead);
- alg = &t_alg->algt.alg.aead.base;
- break;
- }
- if (err) {
- dev_err(dev, "%s alg registration failed\n",
- alg->cra_driver_name);
- devm_kfree(dev, t_alg);
- } else
- list_add_tail(&t_alg->entry, &priv->alg_list);
- }
- }
if (!list_empty(&priv->alg_list))
dev_info(dev, "%s algorithms registered in /proc/crypto\n",
(char *)of_get_property(np, "compatible", NULL));
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 4a803ad6349d..e36a2609d87d 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -21,6 +21,8 @@
#define TALITOS1_MAX_DATA_LEN 32768
#define TALITOS2_MAX_DATA_LEN 65535
+#define TALITOS_CRA_PRIORITY 3000
+
#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
@@ -611,3 +613,4 @@ void talitos_unregister_rng(struct device *dev);
int talitos_register_hash(struct device *dev);
int talitos_register_skcipher(struct device *dev);
+int talitos_register_aead(struct device *dev);
--
2.54.0
^ permalink raw reply related
* [PATCH v2 07/19] crypto: talitos/skcipher - Move into separate file
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Move the skcipher algorithm implementations from talitos.c into
a dedicated talitos-skcipher.c file.
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/Makefile | 2 +-
drivers/crypto/talitos/talitos-skcipher.c | 399 ++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.c | 377 +---------------------------
drivers/crypto/talitos/talitos.h | 1 +
4 files changed, 411 insertions(+), 368 deletions(-)
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
index 40d37f9364ef..d4f19f2f6375 100644
--- a/drivers/crypto/talitos/Makefile
+++ b/drivers/crypto/talitos/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
-talitos-y := talitos.o talitos-rng.o talitos-hash.o
+talitos-y := talitos.o talitos-rng.o talitos-hash.o talitos-skcipher.o
diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/talitos/talitos-skcipher.c
new file mode 100644
index 000000000000..f80373610aa4
--- /dev/null
+++ b/drivers/crypto/talitos/talitos-skcipher.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Freescale SEC (talitos) skcipher implementation
+ *
+ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <crypto/internal/des.h>
+#include <crypto/internal/skcipher.h>
+
+#include "talitos.h"
+
+static void common_nonsnoop_unmap(struct device *dev,
+ struct talitos_edesc *edesc,
+ struct skcipher_request *areq)
+{
+ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
+
+ talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen, 0);
+ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
+
+ if (edesc->dma_len)
+ dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
+ DMA_BIDIRECTIONAL);
+}
+
+static void skcipher_done(struct device *dev,
+ struct talitos_desc *desc, void *context,
+ int err)
+{
+ struct skcipher_request *areq = context;
+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ unsigned int ivsize = crypto_skcipher_ivsize(cipher);
+ struct talitos_edesc *edesc;
+
+ edesc = container_of(desc, struct talitos_edesc, desc);
+
+ common_nonsnoop_unmap(dev, edesc, areq);
+ memcpy(areq->iv, ctx->iv, ivsize);
+
+ kfree(edesc);
+
+ skcipher_request_complete(areq, err);
+}
+
+static int common_nonsnoop(struct talitos_edesc *edesc,
+ struct skcipher_request *areq,
+ void (*callback) (struct device *dev,
+ struct talitos_desc *desc,
+ void *context, int error))
+{
+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ struct device *dev = ctx->dev;
+ struct talitos_desc *desc = &edesc->desc;
+ unsigned int cryptlen = areq->cryptlen;
+ unsigned int ivsize = crypto_skcipher_ivsize(cipher);
+ int sg_count, ret;
+ bool sync_needed = false;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+ bool is_ctr = (desc->hdr & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_AESU &&
+ (desc->hdr & DESC_HDR_MODE0_AESU_MASK) == DESC_HDR_MODE0_AESU_CTR;
+
+ /* first DWORD empty */
+
+ /* cipher iv */
+ to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize, is_sec1);
+
+ /* cipher key */
+ to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, is_sec1);
+
+ sg_count = edesc->src_nents ?: 1;
+ if (is_sec1 && sg_count > 1)
+ sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
+ cryptlen);
+ else
+ sg_count = dma_map_sg(dev, areq->src, sg_count,
+ (areq->src == areq->dst) ?
+ DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
+ /*
+ * cipher in
+ */
+ sg_count = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[3],
+ sg_count, 0, 0, 0, false, is_ctr ? 16 : 1);
+ if (sg_count > 1)
+ sync_needed = true;
+
+ /* cipher out */
+ if (areq->src != areq->dst) {
+ sg_count = edesc->dst_nents ? : 1;
+ if (!is_sec1 || sg_count == 1)
+ dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
+ }
+
+ ret = talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[4],
+ sg_count, 0, (edesc->src_nents + 1));
+ if (ret > 1)
+ sync_needed = true;
+
+ /* iv out */
+ map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv,
+ DMA_FROM_DEVICE);
+
+ /* last DWORD empty */
+
+ if (sync_needed)
+ dma_sync_single_for_device(dev, edesc->dma_link_tbl,
+ edesc->dma_len, DMA_BIDIRECTIONAL);
+
+ ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
+ if (ret != -EINPROGRESS) {
+ common_nonsnoop_unmap(dev, edesc, areq);
+ kfree(edesc);
+ }
+ return ret;
+}
+
+static int skcipher_setkey(struct crypto_skcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ struct device *dev = ctx->dev;
+
+ if (ctx->keylen)
+ dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
+
+ memcpy(&ctx->key, key, keylen);
+ ctx->keylen = keylen;
+
+ ctx->dma_key = dma_map_single(dev, ctx->key, keylen, DMA_TO_DEVICE);
+
+ return 0;
+}
+
+static int skcipher_des_setkey(struct crypto_skcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return verify_skcipher_des_key(cipher, key) ?:
+ skcipher_setkey(cipher, key, keylen);
+}
+
+static int skcipher_des3_setkey(struct crypto_skcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return verify_skcipher_des3_key(cipher, key) ?:
+ skcipher_setkey(cipher, key, keylen);
+}
+
+static int skcipher_aes_setkey(struct crypto_skcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ if (keylen == AES_KEYSIZE_128 || keylen == AES_KEYSIZE_192 ||
+ keylen == AES_KEYSIZE_256)
+ return skcipher_setkey(cipher, key, keylen);
+
+ return -EINVAL;
+}
+
+static struct talitos_edesc *skcipher_edesc_alloc(struct skcipher_request *
+ areq, bool encrypt)
+{
+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ unsigned int ivsize = crypto_skcipher_ivsize(cipher);
+
+ return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
+ areq->iv, 0, areq->cryptlen, 0, ivsize, 0,
+ areq->base.flags, encrypt);
+}
+
+static int skcipher_encrypt(struct skcipher_request *areq)
+{
+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ struct talitos_edesc *edesc;
+ unsigned int blocksize =
+ crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher));
+
+ if (!areq->cryptlen)
+ return 0;
+
+ if (areq->cryptlen % blocksize)
+ return -EINVAL;
+
+ /* allocate extended descriptor */
+ edesc = skcipher_edesc_alloc(areq, true);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+ /* set encrypt */
+ edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
+
+ return common_nonsnoop(edesc, areq, skcipher_done);
+}
+
+static int skcipher_decrypt(struct skcipher_request *areq)
+{
+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ struct talitos_edesc *edesc;
+ unsigned int blocksize =
+ crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher));
+
+ if (!areq->cryptlen)
+ return 0;
+
+ if (areq->cryptlen % blocksize)
+ return -EINVAL;
+
+ /* allocate extended descriptor */
+ edesc = skcipher_edesc_alloc(areq, false);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+ edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
+
+ return common_nonsnoop(edesc, areq, skcipher_done);
+}
+
+static int talitos_cra_init_skcipher(struct crypto_skcipher *tfm)
+{
+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
+ struct talitos_crypto_alg *talitos_alg;
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(tfm);
+
+ talitos_alg = container_of(alg, struct talitos_crypto_alg,
+ algt.alg.skcipher);
+
+ return talitos_init_common(ctx, talitos_alg);
+}
+
+static struct talitos_alg_template skcipher_driver_algs[] = {
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ecb(aes)",
+ .base.cra_driver_name = "ecb-aes-talitos",
+ .base.cra_blocksize = AES_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .setkey = skcipher_aes_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "cbc(aes)",
+ .base.cra_driver_name = "cbc-aes-talitos",
+ .base.cra_blocksize = AES_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+ .setkey = skcipher_aes_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ctr(aes)",
+ .base.cra_driver_name = "ctr-aes-talitos",
+ .base.cra_blocksize = 1,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+ .setkey = skcipher_aes_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_AESU_CTR_NONSNOOP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CTR,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ctr(aes)",
+ .base.cra_driver_name = "ctr-aes-talitos",
+ .base.cra_blocksize = 1,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+ .setkey = skcipher_aes_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CTR,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ecb(des)",
+ .base.cra_driver_name = "ecb-des-talitos",
+ .base.cra_blocksize = DES_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = DES_KEY_SIZE,
+ .max_keysize = DES_KEY_SIZE,
+ .setkey = skcipher_des_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "cbc(des)",
+ .base.cra_driver_name = "cbc-des-talitos",
+ .base.cra_blocksize = DES_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = DES_KEY_SIZE,
+ .max_keysize = DES_KEY_SIZE,
+ .ivsize = DES_BLOCK_SIZE,
+ .setkey = skcipher_des_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ecb(des3_ede)",
+ .base.cra_driver_name = "ecb-3des-talitos",
+ .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = DES3_EDE_KEY_SIZE,
+ .max_keysize = DES3_EDE_KEY_SIZE,
+ .setkey = skcipher_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_3DES,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "cbc(des3_ede)",
+ .base.cra_driver_name = "cbc-3des-talitos",
+ .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = DES3_EDE_KEY_SIZE,
+ .max_keysize = DES3_EDE_KEY_SIZE,
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .setkey = skcipher_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES,
+ },
+};
+
+int talitos_register_skcipher(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ struct skcipher_alg *skcipher_alg;
+ struct crypto_alg *alg;
+ size_t i;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(skcipher_driver_algs); i++) {
+ if (!talitos_hw_supports(
+ dev, skcipher_driver_algs[i].desc_hdr_template))
+ continue;
+
+ skcipher_alg = &skcipher_driver_algs[i].alg.skcipher;
+ alg = &skcipher_alg->base;
+
+ alg->cra_exit = talitos_cra_exit;
+ if (has_ftr_sec1(priv))
+ alg->cra_alignmask = 3;
+
+ skcipher_alg->init = talitos_cra_init_skcipher;
+ skcipher_alg->setkey = skcipher_alg->setkey ?: skcipher_setkey;
+ skcipher_alg->encrypt = skcipher_encrypt;
+ skcipher_alg->decrypt = skcipher_decrypt;
+
+ if (!strcmp(alg->cra_name, "ctr(aes)") && !has_ftr_sec1(priv) &&
+ DESC_TYPE(skcipher_driver_algs[i].desc_hdr_template) !=
+ DESC_TYPE(DESC_HDR_TYPE_AESU_CTR_NONSNOOP)) {
+ continue;
+ }
+
+ ret = talitos_register_common(dev, &skcipher_driver_algs[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 2d5688b1c81e..4b77253e04fa 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -1337,215 +1337,6 @@ static int aead_decrypt(struct aead_request *req)
return ipsec_esp(edesc, req, false, ipsec_esp_decrypt_swauth_done);
}
-static int skcipher_setkey(struct crypto_skcipher *cipher,
- const u8 *key, unsigned int keylen)
-{
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- struct device *dev = ctx->dev;
-
- if (ctx->keylen)
- dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
-
- memcpy(&ctx->key, key, keylen);
- ctx->keylen = keylen;
-
- ctx->dma_key = dma_map_single(dev, ctx->key, keylen, DMA_TO_DEVICE);
-
- return 0;
-}
-
-static int skcipher_des_setkey(struct crypto_skcipher *cipher,
- const u8 *key, unsigned int keylen)
-{
- return verify_skcipher_des_key(cipher, key) ?:
- skcipher_setkey(cipher, key, keylen);
-}
-
-static int skcipher_des3_setkey(struct crypto_skcipher *cipher,
- const u8 *key, unsigned int keylen)
-{
- return verify_skcipher_des3_key(cipher, key) ?:
- skcipher_setkey(cipher, key, keylen);
-}
-
-static int skcipher_aes_setkey(struct crypto_skcipher *cipher,
- const u8 *key, unsigned int keylen)
-{
- if (keylen == AES_KEYSIZE_128 || keylen == AES_KEYSIZE_192 ||
- keylen == AES_KEYSIZE_256)
- return skcipher_setkey(cipher, key, keylen);
-
- return -EINVAL;
-}
-
-static void common_nonsnoop_unmap(struct device *dev,
- struct talitos_edesc *edesc,
- struct skcipher_request *areq)
-{
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
-
- talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen, 0);
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
-
- if (edesc->dma_len)
- dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
- DMA_BIDIRECTIONAL);
-}
-
-static void skcipher_done(struct device *dev,
- struct talitos_desc *desc, void *context,
- int err)
-{
- struct skcipher_request *areq = context;
- struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- unsigned int ivsize = crypto_skcipher_ivsize(cipher);
- struct talitos_edesc *edesc;
-
- edesc = container_of(desc, struct talitos_edesc, desc);
-
- common_nonsnoop_unmap(dev, edesc, areq);
- memcpy(areq->iv, ctx->iv, ivsize);
-
- kfree(edesc);
-
- skcipher_request_complete(areq, err);
-}
-
-static int common_nonsnoop(struct talitos_edesc *edesc,
- struct skcipher_request *areq,
- void (*callback) (struct device *dev,
- struct talitos_desc *desc,
- void *context, int error))
-{
- struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- struct device *dev = ctx->dev;
- struct talitos_desc *desc = &edesc->desc;
- unsigned int cryptlen = areq->cryptlen;
- unsigned int ivsize = crypto_skcipher_ivsize(cipher);
- int sg_count, ret;
- bool sync_needed = false;
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
- bool is_ctr = (desc->hdr & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_AESU &&
- (desc->hdr & DESC_HDR_MODE0_AESU_MASK) == DESC_HDR_MODE0_AESU_CTR;
-
- /* first DWORD empty */
-
- /* cipher iv */
- to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize, is_sec1);
-
- /* cipher key */
- to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, is_sec1);
-
- sg_count = edesc->src_nents ?: 1;
- if (is_sec1 && sg_count > 1)
- sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
- cryptlen);
- else
- sg_count = dma_map_sg(dev, areq->src, sg_count,
- (areq->src == areq->dst) ?
- DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
- /*
- * cipher in
- */
- sg_count = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[3],
- sg_count, 0, 0, 0, false, is_ctr ? 16 : 1);
- if (sg_count > 1)
- sync_needed = true;
-
- /* cipher out */
- if (areq->src != areq->dst) {
- sg_count = edesc->dst_nents ? : 1;
- if (!is_sec1 || sg_count == 1)
- dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
- }
-
- ret = talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[4],
- sg_count, 0, (edesc->src_nents + 1));
- if (ret > 1)
- sync_needed = true;
-
- /* iv out */
- map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv,
- DMA_FROM_DEVICE);
-
- /* last DWORD empty */
-
- if (sync_needed)
- dma_sync_single_for_device(dev, edesc->dma_link_tbl,
- edesc->dma_len, DMA_BIDIRECTIONAL);
-
- ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
- if (ret != -EINPROGRESS) {
- common_nonsnoop_unmap(dev, edesc, areq);
- kfree(edesc);
- }
- return ret;
-}
-
-static struct talitos_edesc *skcipher_edesc_alloc(struct skcipher_request *
- areq, bool encrypt)
-{
- struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- unsigned int ivsize = crypto_skcipher_ivsize(cipher);
-
- return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
- areq->iv, 0, areq->cryptlen, 0, ivsize, 0,
- areq->base.flags, encrypt);
-}
-
-static int skcipher_encrypt(struct skcipher_request *areq)
-{
- struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- struct talitos_edesc *edesc;
- unsigned int blocksize =
- crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher));
-
- if (!areq->cryptlen)
- return 0;
-
- if (areq->cryptlen % blocksize)
- return -EINVAL;
-
- /* allocate extended descriptor */
- edesc = skcipher_edesc_alloc(areq, true);
- if (IS_ERR(edesc))
- return PTR_ERR(edesc);
-
- /* set encrypt */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
-
- return common_nonsnoop(edesc, areq, skcipher_done);
-}
-
-static int skcipher_decrypt(struct skcipher_request *areq)
-{
- struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- struct talitos_edesc *edesc;
- unsigned int blocksize =
- crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher));
-
- if (!areq->cryptlen)
- return 0;
-
- if (areq->cryptlen % blocksize)
- return -EINVAL;
-
- /* allocate extended descriptor */
- edesc = skcipher_edesc_alloc(areq, false);
- if (IS_ERR(edesc))
- return PTR_ERR(edesc);
-
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
-
- return common_nonsnoop(edesc, areq, skcipher_done);
-}
-
static struct talitos_alg_template driver_algs[] = {
/* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
{ .type = CRYPTO_ALG_TYPE_AEAD,
@@ -2004,131 +1795,6 @@ static struct talitos_alg_template driver_algs[] = {
DESC_HDR_MODE1_MDEU_PAD |
DESC_HDR_MODE1_MDEU_MD5_HMAC,
},
- /* SKCIPHER algorithms. */
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(aes)",
- .base.cra_driver_name = "ecb-aes-talitos",
- .base.cra_blocksize = AES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(aes)",
- .base.cra_driver_name = "cbc-aes-talitos",
- .base.cra_blocksize = AES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ctr(aes)",
- .base.cra_driver_name = "ctr-aes-talitos",
- .base.cra_blocksize = 1,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_AESU_CTR_NONSNOOP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CTR,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ctr(aes)",
- .base.cra_driver_name = "ctr-aes-talitos",
- .base.cra_blocksize = 1,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CTR,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(des)",
- .base.cra_driver_name = "ecb-des-talitos",
- .base.cra_blocksize = DES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES_KEY_SIZE,
- .max_keysize = DES_KEY_SIZE,
- .setkey = skcipher_des_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(des)",
- .base.cra_driver_name = "cbc-des-talitos",
- .base.cra_blocksize = DES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES_KEY_SIZE,
- .max_keysize = DES_KEY_SIZE,
- .ivsize = DES_BLOCK_SIZE,
- .setkey = skcipher_des_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(des3_ede)",
- .base.cra_driver_name = "ecb-3des-talitos",
- .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES3_EDE_KEY_SIZE,
- .max_keysize = DES3_EDE_KEY_SIZE,
- .setkey = skcipher_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_3DES,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(des3_ede)",
- .base.cra_driver_name = "cbc-3des-talitos",
- .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES3_EDE_KEY_SIZE,
- .max_keysize = DES3_EDE_KEY_SIZE,
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .setkey = skcipher_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES,
- },
};
int talitos_init_common(struct talitos_ctx *ctx,
@@ -2165,18 +1831,6 @@ static int talitos_cra_init_aead(struct crypto_aead *tfm)
return talitos_init_common(ctx, talitos_alg);
}
-static int talitos_cra_init_skcipher(struct crypto_skcipher *tfm)
-{
- struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
- struct talitos_crypto_alg *talitos_alg;
- struct talitos_ctx *ctx = crypto_skcipher_ctx(tfm);
-
- talitos_alg = container_of(alg, struct talitos_crypto_alg,
- algt.alg.skcipher);
-
- return talitos_init_common(ctx, talitos_alg);
-}
-
void talitos_cra_exit(struct crypto_tfm *tfm)
{
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
@@ -2281,6 +1935,12 @@ int talitos_register_common(struct device *dev,
t_alg->algt.type);
ret = crypto_register_ahash(&t_alg->algt.alg.hash);
break;
+ case CRYPTO_ALG_TYPE_SKCIPHER:
+ alg = &t_alg->algt.alg.skcipher.base;
+ talitos_alg_set_common(priv, alg, t_alg->algt.priority,
+ t_alg->algt.type);
+ ret = crypto_register_skcipher(&t_alg->algt.alg.skcipher);
+ break;
default:
dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
devm_kfree(dev, t_alg);
@@ -2317,21 +1977,6 @@ static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
t_alg->algt = *template;
switch (t_alg->algt.type) {
- case CRYPTO_ALG_TYPE_SKCIPHER:
- alg = &t_alg->algt.alg.skcipher.base;
- alg->cra_exit = talitos_cra_exit;
- t_alg->algt.alg.skcipher.init = talitos_cra_init_skcipher;
- t_alg->algt.alg.skcipher.setkey =
- t_alg->algt.alg.skcipher.setkey ?: skcipher_setkey;
- t_alg->algt.alg.skcipher.encrypt = skcipher_encrypt;
- t_alg->algt.alg.skcipher.decrypt = skcipher_decrypt;
- if (!strcmp(alg->cra_name, "ctr(aes)") && !has_ftr_sec1(priv) &&
- DESC_TYPE(t_alg->algt.desc_hdr_template) !=
- DESC_TYPE(DESC_HDR_TYPE_AESU_CTR_NONSNOOP)) {
- devm_kfree(dev, t_alg);
- return ERR_PTR(-ENOTSUPP);
- }
- break;
case CRYPTO_ALG_TYPE_AEAD:
alg = &t_alg->algt.alg.aead.base;
alg->cra_exit = talitos_cra_exit;
@@ -2578,6 +2223,10 @@ static int talitos_probe(struct platform_device *ofdev)
if (err)
goto err_out;
+ err = talitos_register_skcipher(dev);
+ if (err)
+ goto err_out;
+
/* register crypto algorithms the device supports */
for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
if (talitos_hw_supports(dev,
@@ -2594,12 +2243,6 @@ static int talitos_probe(struct platform_device *ofdev)
}
switch (t_alg->algt.type) {
- case CRYPTO_ALG_TYPE_SKCIPHER:
- err = crypto_register_skcipher(
- &t_alg->algt.alg.skcipher);
- alg = &t_alg->algt.alg.skcipher.base;
- break;
-
case CRYPTO_ALG_TYPE_AEAD:
err = crypto_register_aead(
&t_alg->algt.alg.aead);
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index e59c85e3196c..4a803ad6349d 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -610,3 +610,4 @@ void talitos_unregister_rng(struct device *dev);
/* Hash */
int talitos_register_hash(struct device *dev);
+int talitos_register_skcipher(struct device *dev);
--
2.54.0
^ permalink raw reply related
* [PATCH v2 06/19] crypto: talitos/hash - Move into separate file
From: Paul Louvel @ 2026-06-11 7:36 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Move the ahash algorithm implementations from talitos.c into a dedicated
talitos-hash.c file.
Add a helper that will be called in each crypto implementation file for
registration.
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/Makefile | 2 +-
drivers/crypto/talitos/talitos-hash.c | 830 ++++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.c | 858 +++-------------------------------
drivers/crypto/talitos/talitos.h | 7 +
4 files changed, 901 insertions(+), 796 deletions(-)
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
index 901ec681f010..40d37f9364ef 100644
--- a/drivers/crypto/talitos/Makefile
+++ b/drivers/crypto/talitos/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
-talitos-y := talitos.o talitos-rng.o
+talitos-y := talitos.o talitos-rng.o talitos-hash.o
diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos/talitos-hash.c
new file mode 100644
index 000000000000..76be6b6c6fcc
--- /dev/null
+++ b/drivers/crypto/talitos/talitos-hash.c
@@ -0,0 +1,830 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Freescale SEC (talitos) hash implementation
+ *
+ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <linux/scatterlist.h>
+
+#include <crypto/hash.h>
+#include <crypto/internal/hash.h>
+#include <crypto/md5.h>
+#include <crypto/scatterwalk.h>
+#include <crypto/sha1.h>
+
+#include "talitos.h"
+
+#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
+
+struct talitos_ahash_req_ctx {
+ u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
+ unsigned int hw_context_size;
+ unsigned int swinit;
+ unsigned int first_request;
+ unsigned int last_request;
+ unsigned int to_hash_later;
+};
+
+struct talitos_export_state {
+ u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
+ unsigned int swinit;
+ unsigned int first_request;
+ unsigned int last_request;
+ unsigned int to_hash_later;
+};
+
+static void common_nonsnoop_hash_unmap(struct device *dev,
+ struct talitos_edesc *edesc,
+ struct ahash_request *areq)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+ struct talitos_desc *desc = &edesc->desc;
+
+ unmap_single_talitos_ptr(dev, &desc->ptr[5], DMA_FROM_DEVICE);
+
+ if (edesc->last && req_ctx->last_request)
+ memcpy(areq->result, req_ctx->hw_context,
+ crypto_ahash_digestsize(tfm));
+
+ if (edesc->src)
+ talitos_sg_unmap(dev, edesc, edesc->src, NULL, 0, 0);
+
+ /* When using hashctx-in, must unmap it. */
+ if (from_talitos_ptr_len(&desc->ptr[1], is_sec1))
+ unmap_single_talitos_ptr(dev, &desc->ptr[1],
+ DMA_TO_DEVICE);
+
+ if (edesc->dma_len)
+ dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
+ DMA_BIDIRECTIONAL);
+}
+
+static void free_edesc_list_from(struct ahash_request *areq, struct talitos_edesc *edesc)
+{
+ struct talitos_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
+ struct talitos_edesc *next;
+
+ while (edesc) {
+ next = edesc->next_desc;
+ common_nonsnoop_hash_unmap(ctx->dev, edesc, areq);
+ kfree(edesc);
+ edesc = next;
+ }
+}
+
+static void ahash_done(struct device *dev,
+ struct talitos_desc *desc, void *context,
+ int err)
+{
+ struct ahash_request *areq = context;
+ struct talitos_edesc *edesc =
+ container_of(desc, struct talitos_edesc, desc);
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ bool is_sec1 = has_ftr_sec1(dev_get_drvdata(dev));
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct talitos_edesc *next;
+
+ if (is_sec1) {
+ free_edesc_list_from(areq, edesc);
+ ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
+ } else {
+ next = edesc->next_desc;
+
+ common_nonsnoop_hash_unmap(dev, edesc, areq);
+ kfree(edesc);
+
+ if (err)
+ goto out;
+
+ if (next) {
+ err = talitos_submit(dev, ctx->ch, &next->desc,
+ ahash_done, areq);
+ if (err != -EINPROGRESS)
+ goto out;
+ return;
+ }
+out:
+ if (err && next)
+ free_edesc_list_from(areq, next);
+ ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
+ }
+}
+
+/*
+ * SEC1 doesn't like hashing of 0 sized message, so we do the padding
+ * ourself and submit a padded block
+ */
+static void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
+ struct talitos_edesc *edesc,
+ struct talitos_ptr *ptr)
+{
+ static u8 padded_hash[64] = {
+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ };
+
+ pr_err_once("Bug in SEC1, padding ourself\n");
+ edesc->desc.hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
+ map_single_talitos_ptr(ctx->dev, ptr, sizeof(padded_hash),
+ (char *)padded_hash, DMA_TO_DEVICE);
+}
+
+static void common_nonsnoop_hash(struct talitos_edesc *edesc,
+ struct ahash_request *areq,
+ unsigned int length)
+{
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct device *dev = ctx->dev;
+ struct talitos_desc *desc = &edesc->desc;
+ bool sync_needed = false;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+ int sg_count;
+
+ /* first DWORD empty */
+
+ /* hash context in */
+ if (!edesc->first || !req_ctx->first_request || req_ctx->swinit) {
+ map_single_talitos_ptr_nosync(dev, &desc->ptr[1],
+ req_ctx->hw_context_size,
+ req_ctx->hw_context,
+ DMA_TO_DEVICE);
+ req_ctx->swinit = 0;
+ }
+ /* Indicate next op is not the first. */
+ req_ctx->first_request = 0;
+
+ /* HMAC key */
+ if (ctx->keylen)
+ to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen,
+ is_sec1);
+
+ sg_count = edesc->src_nents ?: 1;
+ if (is_sec1 && sg_count > 1)
+ sg_copy_to_buffer(edesc->src, sg_count, edesc->buf, length);
+ else if (length)
+ sg_count = dma_map_sg(dev, edesc->src, sg_count, DMA_TO_DEVICE);
+
+ /*
+ * data in
+ */
+ sg_count = talitos_sg_map(dev, edesc->src, length, edesc, &desc->ptr[3],
+ sg_count, 0, 0);
+ if (sg_count > 1)
+ sync_needed = true;
+
+ /* fifth DWORD empty */
+
+ /* hash/HMAC out -or- hash context out */
+ if (edesc->last && req_ctx->last_request)
+ map_single_talitos_ptr(dev, &desc->ptr[5],
+ crypto_ahash_digestsize(tfm),
+ req_ctx->hw_context, DMA_FROM_DEVICE);
+ else
+ map_single_talitos_ptr_nosync(dev, &desc->ptr[5],
+ req_ctx->hw_context_size,
+ req_ctx->hw_context,
+ DMA_FROM_DEVICE);
+
+ /* last DWORD empty */
+
+ if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) == 0)
+ talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
+
+ if (sync_needed)
+ dma_sync_single_for_device(dev, edesc->dma_link_tbl,
+ edesc->dma_len, DMA_BIDIRECTIONAL);
+}
+
+static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
+ struct scatterlist *src,
+ unsigned int nbytes)
+{
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+
+ return talitos_edesc_alloc(ctx->dev, src, NULL, NULL, 0,
+ nbytes, 0, 0, 0, areq->base.flags, false);
+}
+
+static struct talitos_edesc *
+ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
+ unsigned int blocksize, bool is_sec1)
+{
+ struct talitos_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct talitos_edesc *first = NULL, *prev_edesc = NULL, *edesc;
+ size_t desc_max = is_sec1 ? TALITOS1_MAX_DATA_LEN :
+ TALITOS2_MAX_DATA_LEN;
+ struct scatterlist tmp[2];
+ size_t to_hash_this_desc;
+ struct scatterlist *src;
+ size_t offset = 0;
+
+ do {
+ src = scatterwalk_ffwd(tmp, areq->src, offset);
+
+ to_hash_this_desc =
+ min(nbytes, ALIGN_DOWN(desc_max, blocksize));
+
+ /* Allocate extended descriptor */
+ edesc = ahash_edesc_alloc(areq, src, to_hash_this_desc);
+ if (IS_ERR(edesc)) {
+ if (first)
+ free_edesc_list_from(areq, first);
+ return edesc;
+ }
+
+ edesc->src = scatterwalk_ffwd(edesc->bufsl, areq->src, offset);
+ edesc->desc.hdr = ctx->desc_hdr_template;
+ edesc->first = offset == 0;
+ edesc->last = nbytes - to_hash_this_desc == 0;
+
+ /* On last one, request SEC to pad; otherwise continue */
+ if (req_ctx->last_request && edesc->last)
+ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
+ else
+ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
+
+ /* request SEC to INIT hash. */
+ if (req_ctx->first_request && edesc->first && !req_ctx->swinit)
+ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
+
+ /*
+ * When the tfm context has a keylen, it's an HMAC.
+ * A first or last (ie. not middle) descriptor must request HMAC.
+ */
+ if (ctx->keylen && ((req_ctx->first_request && edesc->first) ||
+ (req_ctx->last_request && edesc->last)))
+ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
+
+ /* clear the DN bit */
+ if (is_sec1 && !edesc->last)
+ edesc->desc.hdr &= ~DESC_HDR_DONE_NOTIFY;
+
+ common_nonsnoop_hash(edesc, areq, to_hash_this_desc);
+
+ offset += to_hash_this_desc;
+ nbytes -= to_hash_this_desc;
+
+ if (!prev_edesc)
+ first = edesc;
+ else
+ prev_edesc->next_desc = edesc;
+ prev_edesc = edesc;
+ } while (nbytes);
+
+ return first;
+}
+
+static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
+{
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct talitos_edesc *edesc;
+ unsigned int blocksize =
+ crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
+ bool is_sec1 = has_ftr_sec1(dev_get_drvdata(ctx->dev));
+ unsigned int nbytes_to_hash;
+ unsigned int to_hash_later;
+ struct device *dev = ctx->dev;
+ int ret;
+
+ nbytes_to_hash = ALIGN_DOWN(nbytes, blocksize);
+ to_hash_later = nbytes - nbytes_to_hash;
+
+ if (req_ctx->last_request) {
+ nbytes_to_hash = nbytes;
+ to_hash_later = 0;
+ }
+
+ req_ctx->to_hash_later = to_hash_later;
+
+ edesc = ahash_process_req_prepare(areq, nbytes_to_hash, blocksize,
+ is_sec1);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+ ret = talitos_submit(dev, ctx->ch, &edesc->desc, ahash_done, areq);
+ if (ret != -EINPROGRESS)
+ free_edesc_list_from(areq, edesc);
+
+ return ret;
+}
+
+static int ahash_init(struct ahash_request *areq)
+{
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct device *dev = ctx->dev;
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ unsigned int size;
+ dma_addr_t dma;
+
+ /* Initialize the context */
+ req_ctx->first_request = 1;
+ req_ctx->swinit = 0; /* assume h/w init of context */
+ size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
+ ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
+ : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
+ req_ctx->hw_context_size = size;
+ req_ctx->last_request = 0;
+
+ dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
+ DMA_TO_DEVICE);
+ dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
+
+ return 0;
+}
+
+/*
+ * on h/w without explicit sha224 support, we initialize h/w context
+ * manually with sha224 constants, and tell it to run sha256.
+ */
+static int ahash_init_sha224_swinit(struct ahash_request *areq)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+
+ req_ctx->hw_context[0] = SHA224_H0;
+ req_ctx->hw_context[1] = SHA224_H1;
+ req_ctx->hw_context[2] = SHA224_H2;
+ req_ctx->hw_context[3] = SHA224_H3;
+ req_ctx->hw_context[4] = SHA224_H4;
+ req_ctx->hw_context[5] = SHA224_H5;
+ req_ctx->hw_context[6] = SHA224_H6;
+ req_ctx->hw_context[7] = SHA224_H7;
+
+ /* init 64-bit count */
+ req_ctx->hw_context[8] = 0;
+ req_ctx->hw_context[9] = 0;
+
+ ahash_init(areq);
+ req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
+
+ return 0;
+}
+
+static int ahash_update(struct ahash_request *areq)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+
+ req_ctx->last_request = 0;
+
+ return ahash_process_req(areq, areq->nbytes);
+}
+
+static int ahash_final(struct ahash_request *areq)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+
+ req_ctx->last_request = 1;
+
+ return ahash_process_req(areq, 0);
+}
+
+static int ahash_finup(struct ahash_request *areq)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+
+ req_ctx->last_request = 1;
+
+ return ahash_process_req(areq, areq->nbytes);
+}
+
+static int ahash_digest(struct ahash_request *areq)
+{
+ ahash_init(areq);
+ return ahash_finup(areq);
+}
+
+static int ahash_digest_sha224_swinit(struct ahash_request *areq)
+{
+ ahash_init_sha224_swinit(areq);
+ return ahash_finup(areq);
+}
+
+static int ahash_export(struct ahash_request *areq, void *out)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct talitos_export_state *export = out;
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct device *dev = ctx->dev;
+ dma_addr_t dma;
+
+ dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
+ DMA_FROM_DEVICE);
+ dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_FROM_DEVICE);
+
+ memcpy(export->hw_context, req_ctx->hw_context,
+ req_ctx->hw_context_size);
+ export->swinit = req_ctx->swinit;
+ export->first_request = req_ctx->first_request;
+ export->last_request = req_ctx->last_request;
+ export->to_hash_later = req_ctx->to_hash_later;
+
+ return 0;
+}
+
+static int ahash_import(struct ahash_request *areq, const void *in)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct device *dev = ctx->dev;
+ const struct talitos_export_state *export = in;
+ unsigned int size;
+ dma_addr_t dma;
+
+ memset(req_ctx, 0, sizeof(*req_ctx));
+ size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
+ ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
+ : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
+ req_ctx->hw_context_size = size;
+ memcpy(req_ctx->hw_context, export->hw_context, size);
+ req_ctx->swinit = export->swinit;
+ req_ctx->first_request = export->first_request;
+ req_ctx->last_request = export->last_request;
+ req_ctx->to_hash_later = export->to_hash_later;
+
+ dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
+ DMA_TO_DEVICE);
+ dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
+
+ return 0;
+}
+
+static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
+ u8 *hash)
+{
+ struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
+
+ struct scatterlist sg[1];
+ struct ahash_request *req;
+ struct crypto_wait wait;
+ int ret;
+
+ crypto_init_wait(&wait);
+
+ req = ahash_request_alloc(tfm, GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ /* Keep tfm keylen == 0 during hash of the long key */
+ ctx->keylen = 0;
+ ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
+ crypto_req_done, &wait);
+
+ sg_init_one(&sg[0], key, keylen);
+
+ ahash_request_set_crypt(req, sg, hash, keylen);
+ ret = crypto_wait_req(crypto_ahash_digest(req), &wait);
+
+ ahash_request_free(req);
+
+ return ret;
+}
+
+static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
+ unsigned int keylen)
+{
+ struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
+ struct device *dev = ctx->dev;
+ unsigned int blocksize =
+ crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
+ unsigned int digestsize = crypto_ahash_digestsize(tfm);
+ unsigned int keysize = keylen;
+ u8 hash[SHA512_DIGEST_SIZE];
+ int ret;
+
+ if (keylen <= blocksize)
+ memcpy(ctx->key, key, keysize);
+ else {
+ /* Must get the hash of the long key */
+ ret = keyhash(tfm, key, keylen, hash);
+
+ if (ret)
+ return -EINVAL;
+
+ keysize = digestsize;
+ memcpy(ctx->key, hash, digestsize);
+ }
+
+ if (ctx->keylen)
+ dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
+
+ ctx->keylen = keysize;
+ ctx->dma_key = dma_map_single(dev, ctx->key, keysize, DMA_TO_DEVICE);
+
+ return 0;
+}
+
+static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
+{
+ struct crypto_alg *alg = tfm->__crt_alg;
+ struct talitos_crypto_alg *talitos_alg;
+ struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
+
+ talitos_alg = container_of(__crypto_ahash_alg(alg),
+ struct talitos_crypto_alg,
+ algt.alg.hash);
+
+ ctx->keylen = 0;
+
+ return talitos_init_common(ctx, talitos_alg);
+}
+
+static struct talitos_alg_template hash_driver_algs[] = {
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = MD5_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "md5",
+ .cra_driver_name = "md5-talitos",
+ .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_MD5,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA1_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "sha1",
+ .cra_driver_name = "sha1-talitos",
+ .cra_blocksize = SHA1_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA1,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA224_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "sha224",
+ .cra_driver_name = "sha224-talitos",
+ .cra_blocksize = SHA224_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA224,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA256_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "sha256",
+ .cra_driver_name = "sha256-talitos",
+ .cra_blocksize = SHA256_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA256,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA384_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "sha384",
+ .cra_driver_name = "sha384-talitos",
+ .cra_blocksize = SHA384_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA384,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA512_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "sha512",
+ .cra_driver_name = "sha512-talitos",
+ .cra_blocksize = SHA512_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA512,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = MD5_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(md5)",
+ .cra_driver_name = "hmac-md5-talitos",
+ .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_MD5,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA1_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(sha1)",
+ .cra_driver_name = "hmac-sha1-talitos",
+ .cra_blocksize = SHA1_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA1,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA224_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(sha224)",
+ .cra_driver_name = "hmac-sha224-talitos",
+ .cra_blocksize = SHA224_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA224,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA256_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(sha256)",
+ .cra_driver_name = "hmac-sha256-talitos",
+ .cra_blocksize = SHA256_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA256,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA384_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(sha384)",
+ .cra_driver_name = "hmac-sha384-talitos",
+ .cra_blocksize = SHA384_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA384,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA512_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(sha512)",
+ .cra_driver_name = "hmac-sha512-talitos",
+ .cra_blocksize = SHA512_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA512,
+ }
+};
+
+int talitos_register_hash(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ struct ahash_alg *ahash_alg;
+ struct crypto_alg *alg;
+ size_t i;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(hash_driver_algs); i++) {
+ if (!talitos_hw_supports(dev,
+ hash_driver_algs[i].desc_hdr_template))
+ continue;
+
+ ahash_alg = &hash_driver_algs[i].alg.hash;
+ alg = &ahash_alg->halg.base;
+
+ alg->cra_init = talitos_cra_init_ahash;
+ alg->cra_exit = talitos_cra_exit;
+ ahash_alg->init = ahash_init;
+ ahash_alg->update = ahash_update;
+ ahash_alg->final = ahash_final;
+ ahash_alg->finup = ahash_finup;
+ ahash_alg->digest = ahash_digest;
+ if (!strncmp(alg->cra_name, "hmac", 4))
+ ahash_alg->setkey = ahash_setkey;
+ ahash_alg->import = ahash_import;
+ ahash_alg->export = ahash_export;
+
+ if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
+ !strncmp(alg->cra_name, "hmac", 4)) {
+ /* not supported */
+ continue;
+ }
+
+ if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
+ (!strcmp(alg->cra_name, "sha224") ||
+ !strcmp(alg->cra_name, "hmac(sha224)"))) {
+ ahash_alg->init = ahash_init_sha224_swinit;
+ ahash_alg->digest = ahash_digest_sha224_swinit;
+ hash_driver_algs[i].desc_hdr_template =
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA256;
+ }
+
+ ret = talitos_register_common(dev, &hash_driver_algs[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 58e1e534dedd..2d5688b1c81e 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -738,25 +738,6 @@ DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
*/
#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
-#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
-
-struct talitos_ahash_req_ctx {
- u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
- unsigned int hw_context_size;
- unsigned int swinit;
- unsigned int first_request;
- unsigned int last_request;
- unsigned int to_hash_later;
-};
-
-struct talitos_export_state {
- u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
- unsigned int swinit;
- unsigned int first_request;
- unsigned int last_request;
- unsigned int to_hash_later;
-};
-
static int aead_setkey(struct crypto_aead *authenc,
const u8 *key, unsigned int keylen)
{
@@ -1565,501 +1546,6 @@ static int skcipher_decrypt(struct skcipher_request *areq)
return common_nonsnoop(edesc, areq, skcipher_done);
}
-static void common_nonsnoop_hash_unmap(struct device *dev,
- struct talitos_edesc *edesc,
- struct ahash_request *areq)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
- struct talitos_desc *desc = &edesc->desc;
-
- unmap_single_talitos_ptr(dev, &desc->ptr[5], DMA_FROM_DEVICE);
-
- if (edesc->last && req_ctx->last_request)
- memcpy(areq->result, req_ctx->hw_context,
- crypto_ahash_digestsize(tfm));
-
- if (edesc->src)
- talitos_sg_unmap(dev, edesc, edesc->src, NULL, 0, 0);
-
- /* When using hashctx-in, must unmap it. */
- if (from_talitos_ptr_len(&desc->ptr[1], is_sec1))
- unmap_single_talitos_ptr(dev, &desc->ptr[1],
- DMA_TO_DEVICE);
-
- if (edesc->dma_len)
- dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
- DMA_BIDIRECTIONAL);
-}
-
-static void free_edesc_list_from(struct ahash_request *areq, struct talitos_edesc *edesc)
-{
- struct talitos_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
- struct talitos_edesc *next;
-
- while (edesc) {
- next = edesc->next_desc;
- common_nonsnoop_hash_unmap(ctx->dev, edesc, areq);
- kfree(edesc);
- edesc = next;
- }
-}
-
-static void ahash_done(struct device *dev,
- struct talitos_desc *desc, void *context,
- int err)
-{
- struct ahash_request *areq = context;
- struct talitos_edesc *edesc =
- container_of(desc, struct talitos_edesc, desc);
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- bool is_sec1 = has_ftr_sec1(dev_get_drvdata(dev));
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct talitos_edesc *next;
-
- if (is_sec1) {
- free_edesc_list_from(areq, edesc);
- ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
- } else {
- next = edesc->next_desc;
-
- common_nonsnoop_hash_unmap(dev, edesc, areq);
- kfree(edesc);
-
- if (err)
- goto out;
-
- if (next) {
- err = talitos_submit(dev, ctx->ch, &next->desc,
- ahash_done, areq);
- if (err != -EINPROGRESS)
- goto out;
- return;
- }
-out:
- if (err && next)
- free_edesc_list_from(areq, next);
- ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
- }
-}
-
-/*
- * SEC1 doesn't like hashing of 0 sized message, so we do the padding
- * ourself and submit a padded block
- */
-static void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
- struct talitos_edesc *edesc,
- struct talitos_ptr *ptr)
-{
- static u8 padded_hash[64] = {
- 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- };
-
- pr_err_once("Bug in SEC1, padding ourself\n");
- edesc->desc.hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
- map_single_talitos_ptr(ctx->dev, ptr, sizeof(padded_hash),
- (char *)padded_hash, DMA_TO_DEVICE);
-}
-
-static void common_nonsnoop_hash(struct talitos_edesc *edesc,
- struct ahash_request *areq,
- unsigned int length)
-{
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct device *dev = ctx->dev;
- struct talitos_desc *desc = &edesc->desc;
- bool sync_needed = false;
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
- int sg_count;
-
- /* first DWORD empty */
-
- /* hash context in */
- if (!edesc->first || !req_ctx->first_request || req_ctx->swinit) {
- map_single_talitos_ptr_nosync(dev, &desc->ptr[1],
- req_ctx->hw_context_size,
- req_ctx->hw_context,
- DMA_TO_DEVICE);
- req_ctx->swinit = 0;
- }
- /* Indicate next op is not the first. */
- req_ctx->first_request = 0;
-
- /* HMAC key */
- if (ctx->keylen)
- to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen,
- is_sec1);
-
- sg_count = edesc->src_nents ?: 1;
- if (is_sec1 && sg_count > 1)
- sg_copy_to_buffer(edesc->src, sg_count, edesc->buf, length);
- else if (length)
- sg_count = dma_map_sg(dev, edesc->src, sg_count, DMA_TO_DEVICE);
-
- /*
- * data in
- */
- sg_count = talitos_sg_map(dev, edesc->src, length, edesc, &desc->ptr[3],
- sg_count, 0, 0);
- if (sg_count > 1)
- sync_needed = true;
-
- /* fifth DWORD empty */
-
- /* hash/HMAC out -or- hash context out */
- if (edesc->last && req_ctx->last_request)
- map_single_talitos_ptr(dev, &desc->ptr[5],
- crypto_ahash_digestsize(tfm),
- req_ctx->hw_context, DMA_FROM_DEVICE);
- else
- map_single_talitos_ptr_nosync(dev, &desc->ptr[5],
- req_ctx->hw_context_size,
- req_ctx->hw_context,
- DMA_FROM_DEVICE);
-
- /* last DWORD empty */
-
- if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) == 0)
- talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
-
- if (sync_needed)
- dma_sync_single_for_device(dev, edesc->dma_link_tbl,
- edesc->dma_len, DMA_BIDIRECTIONAL);
-}
-
-static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
- struct scatterlist *src,
- unsigned int nbytes)
-{
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
-
- return talitos_edesc_alloc(ctx->dev, src, NULL, NULL, 0,
- nbytes, 0, 0, 0, areq->base.flags, false);
-}
-
-static struct talitos_edesc *
-ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
- unsigned int blocksize, bool is_sec1)
-{
- struct talitos_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct talitos_edesc *first = NULL, *prev_edesc = NULL, *edesc;
- size_t desc_max = is_sec1 ? TALITOS1_MAX_DATA_LEN :
- TALITOS2_MAX_DATA_LEN;
- struct scatterlist tmp[2];
- size_t to_hash_this_desc;
- struct scatterlist *src;
- size_t offset = 0;
-
- do {
- src = scatterwalk_ffwd(tmp, areq->src, offset);
-
- to_hash_this_desc =
- min(nbytes, ALIGN_DOWN(desc_max, blocksize));
-
- /* Allocate extended descriptor */
- edesc = ahash_edesc_alloc(areq, src, to_hash_this_desc);
- if (IS_ERR(edesc)) {
- if (first)
- free_edesc_list_from(areq, first);
- return edesc;
- }
-
- edesc->src = scatterwalk_ffwd(edesc->bufsl, areq->src, offset);
- edesc->desc.hdr = ctx->desc_hdr_template;
- edesc->first = offset == 0;
- edesc->last = nbytes - to_hash_this_desc == 0;
-
- /* On last one, request SEC to pad; otherwise continue */
- if (req_ctx->last_request && edesc->last)
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
- else
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
-
- /* request SEC to INIT hash. */
- if (req_ctx->first_request && edesc->first && !req_ctx->swinit)
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
-
- /*
- * When the tfm context has a keylen, it's an HMAC.
- * A first or last (ie. not middle) descriptor must request HMAC.
- */
- if (ctx->keylen && ((req_ctx->first_request && edesc->first) ||
- (req_ctx->last_request && edesc->last)))
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
-
- /* clear the DN bit */
- if (is_sec1 && !edesc->last)
- edesc->desc.hdr &= ~DESC_HDR_DONE_NOTIFY;
-
- common_nonsnoop_hash(edesc, areq, to_hash_this_desc);
-
- offset += to_hash_this_desc;
- nbytes -= to_hash_this_desc;
-
- if (!prev_edesc)
- first = edesc;
- else
- prev_edesc->next_desc = edesc;
- prev_edesc = edesc;
- } while (nbytes);
-
- return first;
-}
-
-static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
-{
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct talitos_edesc *edesc;
- unsigned int blocksize =
- crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
- bool is_sec1 = has_ftr_sec1(dev_get_drvdata(ctx->dev));
- unsigned int nbytes_to_hash;
- unsigned int to_hash_later;
- struct device *dev = ctx->dev;
- int ret;
-
- nbytes_to_hash = ALIGN_DOWN(nbytes, blocksize);
- to_hash_later = nbytes - nbytes_to_hash;
-
- if (req_ctx->last_request) {
- nbytes_to_hash = nbytes;
- to_hash_later = 0;
- }
-
- req_ctx->to_hash_later = to_hash_later;
-
- edesc = ahash_process_req_prepare(areq, nbytes_to_hash, blocksize,
- is_sec1);
- if (IS_ERR(edesc))
- return PTR_ERR(edesc);
-
- ret = talitos_submit(dev, ctx->ch, &edesc->desc, ahash_done, areq);
- if (ret != -EINPROGRESS)
- free_edesc_list_from(areq, edesc);
-
- return ret;
-}
-
-static int ahash_init(struct ahash_request *areq)
-{
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct device *dev = ctx->dev;
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- unsigned int size;
- dma_addr_t dma;
-
- /* Initialize the context */
- req_ctx->first_request = 1;
- req_ctx->swinit = 0; /* assume h/w init of context */
- size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
- ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
- : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
- req_ctx->hw_context_size = size;
- req_ctx->last_request = 0;
-
- dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
- DMA_TO_DEVICE);
- dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
-
- return 0;
-}
-
-/*
- * on h/w without explicit sha224 support, we initialize h/w context
- * manually with sha224 constants, and tell it to run sha256.
- */
-static int ahash_init_sha224_swinit(struct ahash_request *areq)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
-
- req_ctx->hw_context[0] = SHA224_H0;
- req_ctx->hw_context[1] = SHA224_H1;
- req_ctx->hw_context[2] = SHA224_H2;
- req_ctx->hw_context[3] = SHA224_H3;
- req_ctx->hw_context[4] = SHA224_H4;
- req_ctx->hw_context[5] = SHA224_H5;
- req_ctx->hw_context[6] = SHA224_H6;
- req_ctx->hw_context[7] = SHA224_H7;
-
- /* init 64-bit count */
- req_ctx->hw_context[8] = 0;
- req_ctx->hw_context[9] = 0;
-
- ahash_init(areq);
- req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
-
- return 0;
-}
-
-static int ahash_update(struct ahash_request *areq)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
-
- req_ctx->last_request = 0;
-
- return ahash_process_req(areq, areq->nbytes);
-}
-
-static int ahash_final(struct ahash_request *areq)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
-
- req_ctx->last_request = 1;
-
- return ahash_process_req(areq, 0);
-}
-
-static int ahash_finup(struct ahash_request *areq)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
-
- req_ctx->last_request = 1;
-
- return ahash_process_req(areq, areq->nbytes);
-}
-
-static int ahash_digest(struct ahash_request *areq)
-{
- ahash_init(areq);
- return ahash_finup(areq);
-}
-
-static int ahash_digest_sha224_swinit(struct ahash_request *areq)
-{
- ahash_init_sha224_swinit(areq);
- return ahash_finup(areq);
-}
-
-static int ahash_export(struct ahash_request *areq, void *out)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct talitos_export_state *export = out;
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct device *dev = ctx->dev;
- dma_addr_t dma;
-
- dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
- DMA_FROM_DEVICE);
- dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_FROM_DEVICE);
-
- memcpy(export->hw_context, req_ctx->hw_context,
- req_ctx->hw_context_size);
- export->swinit = req_ctx->swinit;
- export->first_request = req_ctx->first_request;
- export->last_request = req_ctx->last_request;
- export->to_hash_later = req_ctx->to_hash_later;
-
- return 0;
-}
-
-static int ahash_import(struct ahash_request *areq, const void *in)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct device *dev = ctx->dev;
- const struct talitos_export_state *export = in;
- unsigned int size;
- dma_addr_t dma;
-
- memset(req_ctx, 0, sizeof(*req_ctx));
- size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
- ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
- : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
- req_ctx->hw_context_size = size;
- memcpy(req_ctx->hw_context, export->hw_context, size);
- req_ctx->swinit = export->swinit;
- req_ctx->first_request = export->first_request;
- req_ctx->last_request = export->last_request;
- req_ctx->to_hash_later = export->to_hash_later;
-
- dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
- DMA_TO_DEVICE);
- dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
-
- return 0;
-}
-
-static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
- u8 *hash)
-{
- struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
-
- struct scatterlist sg[1];
- struct ahash_request *req;
- struct crypto_wait wait;
- int ret;
-
- crypto_init_wait(&wait);
-
- req = ahash_request_alloc(tfm, GFP_KERNEL);
- if (!req)
- return -ENOMEM;
-
- /* Keep tfm keylen == 0 during hash of the long key */
- ctx->keylen = 0;
- ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
- crypto_req_done, &wait);
-
- sg_init_one(&sg[0], key, keylen);
-
- ahash_request_set_crypt(req, sg, hash, keylen);
- ret = crypto_wait_req(crypto_ahash_digest(req), &wait);
-
- ahash_request_free(req);
-
- return ret;
-}
-
-static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
- unsigned int keylen)
-{
- struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
- struct device *dev = ctx->dev;
- unsigned int blocksize =
- crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
- unsigned int digestsize = crypto_ahash_digestsize(tfm);
- unsigned int keysize = keylen;
- u8 hash[SHA512_DIGEST_SIZE];
- int ret;
-
- if (keylen <= blocksize)
- memcpy(ctx->key, key, keysize);
- else {
- /* Must get the hash of the long key */
- ret = keyhash(tfm, key, keylen, hash);
-
- if (ret)
- return -EINVAL;
-
- keysize = digestsize;
- memcpy(ctx->key, hash, digestsize);
- }
-
- if (ctx->keylen)
- dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
-
- ctx->keylen = keysize;
- ctx->dma_key = dma_map_single(dev, ctx->key, keysize, DMA_TO_DEVICE);
-
- return 0;
-}
-
static struct talitos_alg_template driver_algs[] = {
/* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
{ .type = CRYPTO_ALG_TYPE_AEAD,
@@ -2643,235 +2129,6 @@ static struct talitos_alg_template driver_algs[] = {
DESC_HDR_MODE0_DEU_CBC |
DESC_HDR_MODE0_DEU_3DES,
},
- /* AHASH algorithms. */
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = MD5_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "md5",
- .cra_driver_name = "md5-talitos",
- .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_MD5,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA1_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha1",
- .cra_driver_name = "sha1-talitos",
- .cra_blocksize = SHA1_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA1,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA224_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha224",
- .cra_driver_name = "sha224-talitos",
- .cra_blocksize = SHA224_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA224,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA256_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha256",
- .cra_driver_name = "sha256-talitos",
- .cra_blocksize = SHA256_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA256,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA384_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha384",
- .cra_driver_name = "sha384-talitos",
- .cra_blocksize = SHA384_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA384,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA512_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha512",
- .cra_driver_name = "sha512-talitos",
- .cra_blocksize = SHA512_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA512,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = MD5_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(md5)",
- .cra_driver_name = "hmac-md5-talitos",
- .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_MD5,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA1_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha1)",
- .cra_driver_name = "hmac-sha1-talitos",
- .cra_blocksize = SHA1_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA1,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA224_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha224)",
- .cra_driver_name = "hmac-sha224-talitos",
- .cra_blocksize = SHA224_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA224,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA256_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha256)",
- .cra_driver_name = "hmac-sha256-talitos",
- .cra_blocksize = SHA256_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA256,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA384_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha384)",
- .cra_driver_name = "hmac-sha384-talitos",
- .cra_blocksize = SHA384_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA384,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA512_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha512)",
- .cra_driver_name = "hmac-sha512-talitos",
- .cra_blocksize = SHA512_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA512,
- }
};
int talitos_init_common(struct talitos_ctx *ctx,
@@ -2920,21 +2177,6 @@ static int talitos_cra_init_skcipher(struct crypto_skcipher *tfm)
return talitos_init_common(ctx, talitos_alg);
}
-static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
-{
- struct crypto_alg *alg = tfm->__crt_alg;
- struct talitos_crypto_alg *talitos_alg;
- struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
-
- talitos_alg = container_of(__crypto_ahash_alg(alg),
- struct talitos_crypto_alg,
- algt.alg.hash);
-
- ctx->keylen = 0;
-
- return talitos_init_common(ctx, talitos_alg);
-}
-
void talitos_cra_exit(struct crypto_tfm *tfm)
{
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
@@ -3000,6 +2242,65 @@ static void talitos_remove(struct platform_device *ofdev)
tasklet_kill(&priv->done_task[1]);
}
+static void talitos_alg_set_common(struct talitos_private *priv,
+ struct crypto_alg *alg, u32 custom_priority,
+ u32 type)
+{
+ alg->cra_module = THIS_MODULE;
+ if (custom_priority)
+ alg->cra_priority = custom_priority;
+ else
+ alg->cra_priority = TALITOS_CRA_PRIORITY;
+ if (has_ftr_sec1(priv) && type != CRYPTO_ALG_TYPE_AHASH)
+ alg->cra_alignmask = 3;
+ else
+ alg->cra_alignmask = 0;
+ alg->cra_ctxsize = sizeof(struct talitos_ctx);
+ alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
+}
+
+int talitos_register_common(struct device *dev,
+ struct talitos_alg_template *template)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ struct talitos_crypto_alg *t_alg;
+ struct crypto_alg *alg;
+ int ret;
+
+ t_alg = devm_kzalloc(dev, sizeof(struct talitos_crypto_alg),
+ GFP_KERNEL);
+ if (!t_alg)
+ return -ENOMEM;
+
+ t_alg->algt = *template;
+
+ switch (t_alg->algt.type) {
+ case CRYPTO_ALG_TYPE_AHASH:
+ alg = &t_alg->algt.alg.hash.halg.base;
+ talitos_alg_set_common(priv, alg, t_alg->algt.priority,
+ t_alg->algt.type);
+ ret = crypto_register_ahash(&t_alg->algt.alg.hash);
+ break;
+ default:
+ dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
+ devm_kfree(dev, t_alg);
+ return -EINVAL;
+ }
+
+ if (ret) {
+ dev_err(dev, "%s alg registration failed\n",
+ alg->cra_driver_name);
+ devm_kfree(dev, t_alg);
+ return 0;
+ }
+
+ t_alg->dev = dev;
+
+ list_add_tail(&t_alg->entry, &priv->alg_list);
+
+ return 0;
+}
+
static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
struct talitos_alg_template
*template)
@@ -3045,37 +2346,6 @@ static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
return ERR_PTR(-ENOTSUPP);
}
break;
- case CRYPTO_ALG_TYPE_AHASH:
- alg = &t_alg->algt.alg.hash.halg.base;
- alg->cra_init = talitos_cra_init_ahash;
- alg->cra_exit = talitos_cra_exit;
- t_alg->algt.alg.hash.init = ahash_init;
- t_alg->algt.alg.hash.update = ahash_update;
- t_alg->algt.alg.hash.final = ahash_final;
- t_alg->algt.alg.hash.finup = ahash_finup;
- t_alg->algt.alg.hash.digest = ahash_digest;
- if (!strncmp(alg->cra_name, "hmac", 4))
- t_alg->algt.alg.hash.setkey = ahash_setkey;
- t_alg->algt.alg.hash.import = ahash_import;
- t_alg->algt.alg.hash.export = ahash_export;
-
- if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
- !strncmp(alg->cra_name, "hmac", 4)) {
- devm_kfree(dev, t_alg);
- return ERR_PTR(-ENOTSUPP);
- }
- if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
- (!strcmp(alg->cra_name, "sha224") ||
- !strcmp(alg->cra_name, "hmac(sha224)"))) {
- t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
- t_alg->algt.alg.hash.digest =
- ahash_digest_sha224_swinit;
- t_alg->algt.desc_hdr_template =
- DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA256;
- }
- break;
default:
dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
devm_kfree(dev, t_alg);
@@ -3304,6 +2574,10 @@ static int talitos_probe(struct platform_device *ofdev)
dev_info(dev, "hwrng\n");
}
+ err = talitos_register_hash(dev);
+ if (err)
+ goto err_out;
+
/* register crypto algorithms the device supports */
for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
if (talitos_hw_supports(dev,
@@ -3331,12 +2605,6 @@ static int talitos_probe(struct platform_device *ofdev)
&t_alg->algt.alg.aead);
alg = &t_alg->algt.alg.aead.base;
break;
-
- case CRYPTO_ALG_TYPE_AHASH:
- err = crypto_register_ahash(
- &t_alg->algt.alg.hash);
- alg = &t_alg->algt.alg.hash.halg.base;
- break;
}
if (err) {
dev_err(dev, "%s alg registration failed\n",
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 81331914801b..e59c85e3196c 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -599,7 +599,14 @@ int talitos_init_common(struct talitos_ctx *ctx,
struct talitos_crypto_alg *talitos_alg);
void talitos_cra_exit(struct crypto_tfm *tfm);
+int talitos_register_common(struct device *dev,
+ struct talitos_alg_template *template);
+
/* Hardware RNG */
int talitos_register_rng(struct device *dev);
void talitos_unregister_rng(struct device *dev);
+
+/* Hash */
+
+int talitos_register_hash(struct device *dev);
--
2.54.0
^ permalink raw reply related
* [PATCH v2 05/19] crypto: talitos - Prepare crypto implementation file splitting
From: Paul Louvel @ 2026-06-11 7:35 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Move all talitos helpers and inline them inside the header file.
Remove the static qualifier for the core functions of the driver, they
will be called inside each crypto implementation file.
Add the common structures too.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 182 ++++++---------------------------------
drivers/crypto/talitos/talitos.h | 167 +++++++++++++++++++++++++++++++++++
2 files changed, 194 insertions(+), 155 deletions(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index e28c60d17bb5..58e1e534dedd 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -40,99 +40,6 @@
#include "talitos.h"
-static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
- unsigned int len, bool is_sec1)
-{
- ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
- if (is_sec1) {
- ptr->len1 = cpu_to_be16(len);
- } else {
- ptr->len = cpu_to_be16(len);
- ptr->eptr = upper_32_bits(dma_addr);
- }
-}
-
-static void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
- struct talitos_ptr *src_ptr, bool is_sec1)
-{
- dst_ptr->ptr = src_ptr->ptr;
- if (is_sec1) {
- dst_ptr->len1 = src_ptr->len1;
- } else {
- dst_ptr->len = src_ptr->len;
- dst_ptr->eptr = src_ptr->eptr;
- }
-}
-
-static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
- bool is_sec1)
-{
- if (is_sec1)
- return be16_to_cpu(ptr->len1);
- else
- return be16_to_cpu(ptr->len);
-}
-
-static void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
- bool is_sec1)
-{
- if (!is_sec1)
- ptr->j_extent = val;
-}
-
-static void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1)
-{
- if (!is_sec1)
- ptr->j_extent |= val;
-}
-
-/*
- * map virtual single (contiguous) pointer to h/w descriptor pointer
- */
-static void __map_single_talitos_ptr(struct device *dev,
- struct talitos_ptr *ptr,
- unsigned int len, void *data,
- enum dma_data_direction dir,
- unsigned long attrs)
-{
- dma_addr_t dma_addr = dma_map_single_attrs(dev, data, len, dir, attrs);
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
-
- to_talitos_ptr(ptr, dma_addr, len, is_sec1);
-}
-
-static void map_single_talitos_ptr(struct device *dev,
- struct talitos_ptr *ptr,
- unsigned int len, void *data,
- enum dma_data_direction dir)
-{
- __map_single_talitos_ptr(dev, ptr, len, data, dir, 0);
-}
-
-static void map_single_talitos_ptr_nosync(struct device *dev,
- struct talitos_ptr *ptr,
- unsigned int len, void *data,
- enum dma_data_direction dir)
-{
- __map_single_talitos_ptr(dev, ptr, len, data, dir,
- DMA_ATTR_SKIP_CPU_SYNC);
-}
-
-/*
- * unmap bus single (contiguous) h/w descriptor pointer
- */
-static void unmap_single_talitos_ptr(struct device *dev,
- struct talitos_ptr *ptr,
- enum dma_data_direction dir)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
-
- dma_unmap_single(dev, be32_to_cpu(ptr->ptr),
- from_talitos_ptr_len(ptr, is_sec1), dir);
-}
-
static int reset_channel(struct device *dev, int ch)
{
struct talitos_private *priv = dev_get_drvdata(dev);
@@ -303,11 +210,11 @@ static void dma_map_request(struct device *dev, struct talitos_request *request,
* callback must check err and feedback in descriptor header
* for device processing status.
*/
-static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
- void (*callback)(struct device *dev,
- struct talitos_desc *desc,
- void *context, int error),
- void *context)
+int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
+ void (*callback)(struct device *dev,
+ struct talitos_desc *desc,
+ void *context, int error),
+ void *context)
{
struct talitos_private *priv = dev_get_drvdata(dev);
struct talitos_request *request;
@@ -830,24 +737,6 @@ DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
* HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP
*/
#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
-#ifdef CONFIG_CRYPTO_DEV_TALITOS2
-#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE)
-#else
-#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA256_BLOCK_SIZE)
-#endif
-#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
-
-struct talitos_ctx {
- struct device *dev;
- int ch;
- __be32 desc_hdr_template;
- u8 key[TALITOS_MAX_KEY_SIZE];
- u8 iv[TALITOS_MAX_IV_LENGTH];
- dma_addr_t dma_key;
- unsigned int keylen;
- unsigned int enckeylen;
- unsigned int authkeylen;
-};
#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
@@ -938,7 +827,7 @@ static int aead_des3_setkey(struct crypto_aead *authenc,
return err;
}
-static void talitos_sg_unmap(struct device *dev,
+void talitos_sg_unmap(struct device *dev,
struct talitos_edesc *edesc,
struct scatterlist *src,
struct scatterlist *dst,
@@ -1123,7 +1012,7 @@ static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
return count;
}
-static int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
+int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
unsigned int len, struct talitos_edesc *edesc,
struct talitos_ptr *ptr, int sg_count,
unsigned int offset, int tbl_off, int elen,
@@ -1160,7 +1049,7 @@ static int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
return sg_count;
}
-static int talitos_sg_map(struct device *dev, struct scatterlist *src,
+int talitos_sg_map(struct device *dev, struct scatterlist *src,
unsigned int len, struct talitos_edesc *edesc,
struct talitos_ptr *ptr, int sg_count,
unsigned int offset, int tbl_off)
@@ -1298,17 +1187,17 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
/*
* allocate and map the extended descriptor
*/
-static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
- struct scatterlist *src,
- struct scatterlist *dst,
- u8 *iv,
- unsigned int assoclen,
- unsigned int cryptlen,
- unsigned int authsize,
- unsigned int ivsize,
- int icv_stashing,
- u32 cryptoflags,
- bool encrypt)
+struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
+ struct scatterlist *src,
+ struct scatterlist *dst,
+ u8 *iv,
+ unsigned int assoclen,
+ unsigned int cryptlen,
+ unsigned int authsize,
+ unsigned int ivsize,
+ int icv_stashing,
+ u32 cryptoflags,
+ bool encrypt)
{
struct talitos_edesc *edesc;
int src_nents, dst_nents, alloc_len, dma_len, src_len, dst_len;
@@ -2171,18 +2060,6 @@ static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
return 0;
}
-
-struct talitos_alg_template {
- u32 type;
- u32 priority;
- union {
- struct skcipher_alg skcipher;
- struct ahash_alg hash;
- struct aead_alg aead;
- } alg;
- __be32 desc_hdr_template;
-};
-
static struct talitos_alg_template driver_algs[] = {
/* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
{ .type = CRYPTO_ALG_TYPE_AEAD,
@@ -2997,14 +2874,8 @@ static struct talitos_alg_template driver_algs[] = {
}
};
-struct talitos_crypto_alg {
- struct list_head entry;
- struct device *dev;
- struct talitos_alg_template algt;
-};
-
-static int talitos_init_common(struct talitos_ctx *ctx,
- struct talitos_crypto_alg *talitos_alg)
+int talitos_init_common(struct talitos_ctx *ctx,
+ struct talitos_crypto_alg *talitos_alg)
{
struct talitos_private *priv;
@@ -3064,7 +2935,7 @@ static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
return talitos_init_common(ctx, talitos_alg);
}
-static void talitos_cra_exit(struct crypto_tfm *tfm)
+void talitos_cra_exit(struct crypto_tfm *tfm)
{
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
struct device *dev = ctx->dev;
@@ -3078,7 +2949,7 @@ static void talitos_cra_exit(struct crypto_tfm *tfm)
* type and primary/secondary execution units required match the hw
* capabilities description provided in the device tree node.
*/
-static int hw_supports(struct device *dev, __be32 desc_hdr_template)
+int talitos_hw_supports(struct device *dev, __be32 desc_hdr_template)
{
struct talitos_private *priv = dev_get_drvdata(dev);
int ret;
@@ -3115,7 +2986,7 @@ static void talitos_remove(struct platform_device *ofdev)
list_del(&t_alg->entry);
}
- if (hw_supports(dev, DESC_HDR_SEL0_RNG))
+ if (talitos_hw_supports(dev, DESC_HDR_SEL0_RNG))
talitos_unregister_rng(dev);
for (i = 0; i < 2; i++)
@@ -3424,7 +3295,7 @@ static int talitos_probe(struct platform_device *ofdev)
}
/* register the RNG, if available */
- if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
+ if (talitos_hw_supports(dev, DESC_HDR_SEL0_RNG)) {
err = talitos_register_rng(dev);
if (err) {
dev_err(dev, "failed to register hwrng: %d\n", err);
@@ -3435,7 +3306,8 @@ static int talitos_probe(struct platform_device *ofdev)
/* register crypto algorithms the device supports */
for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
- if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
+ if (talitos_hw_supports(dev,
+ driver_algs[i].desc_hdr_template)) {
struct talitos_crypto_alg *t_alg;
struct crypto_alg *alg = NULL;
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index fa8c71b1f90f..81331914801b 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -5,7 +5,13 @@
* Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
*/
+#include <crypto/aes.h>
+#include <crypto/internal/aead.h>
+#include <crypto/internal/hash.h>
+#include <crypto/internal/skcipher.h>
+#include <crypto/sha2.h>
#include <linux/device.h>
+#include <linux/dma-mapping.h>
#include <linux/hw_random.h>
#include <linux/interrupt.h>
#include <linux/scatterlist.h>
@@ -19,6 +25,13 @@
#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
+#ifdef CONFIG_CRYPTO_DEV_TALITOS2
+#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE)
+#else
+#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA256_BLOCK_SIZE)
+#endif
+#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
+
/* descriptor pointer entry */
struct talitos_ptr {
union {
@@ -174,6 +187,35 @@ struct talitos_private {
};
+struct talitos_ctx {
+ struct device *dev;
+ int ch;
+ __be32 desc_hdr_template;
+ u8 key[TALITOS_MAX_KEY_SIZE];
+ u8 iv[TALITOS_MAX_IV_LENGTH];
+ dma_addr_t dma_key;
+ unsigned int keylen;
+ unsigned int enckeylen;
+ unsigned int authkeylen;
+};
+
+struct talitos_alg_template {
+ u32 type;
+ u32 priority;
+ union {
+ struct skcipher_alg skcipher;
+ struct ahash_alg hash;
+ struct aead_alg aead;
+ } alg;
+ __be32 desc_hdr_template;
+};
+
+struct talitos_crypto_alg {
+ struct list_head entry;
+ struct device *dev;
+ struct talitos_alg_template algt;
+};
+
/* .features flag */
#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
@@ -432,6 +474,131 @@ static inline bool has_ftr_sec1(struct talitos_private *priv)
#define DESC_PTR_LNKTBL_RET 0x02
#define DESC_PTR_LNKTBL_NEXT 0x01
+static inline void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
+ unsigned int len, bool is_sec1)
+{
+ ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
+ if (is_sec1) {
+ ptr->len1 = cpu_to_be16(len);
+ } else {
+ ptr->len = cpu_to_be16(len);
+ ptr->eptr = upper_32_bits(dma_addr);
+ }
+}
+
+static inline void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
+ struct talitos_ptr *src_ptr, bool is_sec1)
+{
+ dst_ptr->ptr = src_ptr->ptr;
+ if (is_sec1) {
+ dst_ptr->len1 = src_ptr->len1;
+ } else {
+ dst_ptr->len = src_ptr->len;
+ dst_ptr->eptr = src_ptr->eptr;
+ }
+}
+
+static inline unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
+ bool is_sec1)
+{
+ if (is_sec1)
+ return be16_to_cpu(ptr->len1);
+ else
+ return be16_to_cpu(ptr->len);
+}
+
+static inline void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
+ bool is_sec1)
+{
+ if (!is_sec1)
+ ptr->j_extent = val;
+}
+
+static inline void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val,
+ bool is_sec1)
+{
+ if (!is_sec1)
+ ptr->j_extent |= val;
+}
+
+/*
+ * map virtual single (contiguous) pointer to h/w descriptor pointer
+ */
+static void __map_single_talitos_ptr(struct device *dev,
+ struct talitos_ptr *ptr, unsigned int len,
+ void *data, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ dma_addr_t dma_addr = dma_map_single_attrs(dev, data, len, dir, attrs);
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+
+ to_talitos_ptr(ptr, dma_addr, len, is_sec1);
+}
+
+static inline void map_single_talitos_ptr(struct device *dev,
+ struct talitos_ptr *ptr,
+ unsigned int len, void *data,
+ enum dma_data_direction dir)
+{
+ __map_single_talitos_ptr(dev, ptr, len, data, dir, 0);
+}
+
+static inline void map_single_talitos_ptr_nosync(struct device *dev,
+ struct talitos_ptr *ptr,
+ unsigned int len, void *data,
+ enum dma_data_direction dir)
+{
+ __map_single_talitos_ptr(dev, ptr, len, data, dir,
+ DMA_ATTR_SKIP_CPU_SYNC);
+}
+
+/*
+ * unmap bus single (contiguous) h/w descriptor pointer
+ */
+static inline void unmap_single_talitos_ptr(struct device *dev,
+ struct talitos_ptr *ptr,
+ enum dma_data_direction dir)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+
+ dma_unmap_single(dev, be32_to_cpu(ptr->ptr),
+ from_talitos_ptr_len(ptr, is_sec1), dir);
+}
+
+int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
+ void (*callback)(struct device *dev,
+ struct talitos_desc *desc, void *context,
+ int error),
+ void *context);
+
+void talitos_sg_unmap(struct device *dev, struct talitos_edesc *edesc,
+ struct scatterlist *src, struct scatterlist *dst,
+ unsigned int len, unsigned int offset);
+int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
+ unsigned int len, struct talitos_edesc *edesc,
+ struct talitos_ptr *ptr, int sg_count,
+ unsigned int offset, int tbl_off, int elen, bool force,
+ int align);
+int talitos_sg_map(struct device *dev, struct scatterlist *src,
+ unsigned int len, struct talitos_edesc *edesc,
+ struct talitos_ptr *ptr, int sg_count, unsigned int offset,
+ int tbl_off);
+
+struct talitos_edesc *
+talitos_edesc_alloc(struct device *dev, struct scatterlist *src,
+ struct scatterlist *dst, u8 *iv, unsigned int assoclen,
+ unsigned int cryptlen, unsigned int authsize,
+ unsigned int ivsize, int icv_stashing, u32 cryptoflags,
+ bool encrypt);
+
+int talitos_hw_supports(struct device *dev, __be32 desc_hdr_template);
+
+int talitos_init_common(struct talitos_ctx *ctx,
+ struct talitos_crypto_alg *talitos_alg);
+void talitos_cra_exit(struct crypto_tfm *tfm);
+
/* Hardware RNG */
int talitos_register_rng(struct device *dev);
--
2.54.0
^ permalink raw reply related
* [PATCH v2 04/19] crypto: talitos/hwrng - Move into separate file
From: Paul Louvel @ 2026-06-11 7:35 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Move the hardware random number generator implementation from
talitos.c into a dedicated talitos-rng.c file.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/Makefile | 2 +
drivers/crypto/talitos/talitos-rng.c | 93 ++++++++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.c | 83 --------------------------------
drivers/crypto/talitos/talitos.h | 5 ++
4 files changed, 100 insertions(+), 83 deletions(-)
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
index fcc5db5e63c2..901ec681f010 100644
--- a/drivers/crypto/talitos/Makefile
+++ b/drivers/crypto/talitos/Makefile
@@ -1 +1,3 @@
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
+
+talitos-y := talitos.o talitos-rng.o
diff --git a/drivers/crypto/talitos/talitos-rng.c b/drivers/crypto/talitos/talitos-rng.c
new file mode 100644
index 000000000000..3aa00de33b25
--- /dev/null
+++ b/drivers/crypto/talitos/talitos-rng.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Freescale SEC (talitos) device hardware random number generator implementation
+ *
+ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include "talitos.h"
+
+static int talitos_rng_data_present(struct hwrng *rng, int wait)
+{
+ struct device *dev = (struct device *)rng->priv;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ u32 ofl;
+ int i;
+
+ for (i = 0; i < 20; i++) {
+ ofl = in_be32(priv->reg_rngu + TALITOS_EUSR_LO) &
+ TALITOS_RNGUSR_LO_OFL;
+ if (ofl || !wait)
+ break;
+ udelay(10);
+ }
+
+ return !!ofl;
+}
+
+static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
+{
+ struct device *dev = (struct device *)rng->priv;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ /* rng fifo requires 64-bit accesses */
+ *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO);
+ *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO);
+
+ return sizeof(u32);
+}
+
+static int talitos_rng_init(struct hwrng *rng)
+{
+ struct device *dev = (struct device *)rng->priv;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ unsigned int timeout = TALITOS_TIMEOUT;
+
+ setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR);
+ while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO)
+ & TALITOS_RNGUSR_LO_RD)
+ && --timeout)
+ cpu_relax();
+ if (timeout == 0) {
+ dev_err(dev, "failed to reset rng hw\n");
+ return -ENODEV;
+ }
+
+ /* start generating */
+ setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0);
+
+ return 0;
+}
+
+int talitos_register_rng(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ int err;
+
+ priv->rng.name = dev_driver_string(dev);
+ priv->rng.init = talitos_rng_init;
+ priv->rng.data_present = talitos_rng_data_present;
+ priv->rng.data_read = talitos_rng_data_read;
+ priv->rng.priv = (unsigned long)dev;
+
+ err = hwrng_register(&priv->rng);
+ if (!err)
+ priv->rng_registered = true;
+
+ return err;
+}
+
+void talitos_unregister_rng(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ if (!priv->rng_registered)
+ return;
+
+ hwrng_unregister(&priv->rng);
+ priv->rng_registered = false;
+}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 58663edd4ad4..e28c60d17bb5 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -820,89 +820,6 @@ DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE, TALITOS2_ISR_CH_0_2_ERR,
DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
1)
-/*
- * hwrng
- */
-static int talitos_rng_data_present(struct hwrng *rng, int wait)
-{
- struct device *dev = (struct device *)rng->priv;
- struct talitos_private *priv = dev_get_drvdata(dev);
- u32 ofl;
- int i;
-
- for (i = 0; i < 20; i++) {
- ofl = in_be32(priv->reg_rngu + TALITOS_EUSR_LO) &
- TALITOS_RNGUSR_LO_OFL;
- if (ofl || !wait)
- break;
- udelay(10);
- }
-
- return !!ofl;
-}
-
-static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
-{
- struct device *dev = (struct device *)rng->priv;
- struct talitos_private *priv = dev_get_drvdata(dev);
-
- /* rng fifo requires 64-bit accesses */
- *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO);
- *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO);
-
- return sizeof(u32);
-}
-
-static int talitos_rng_init(struct hwrng *rng)
-{
- struct device *dev = (struct device *)rng->priv;
- struct talitos_private *priv = dev_get_drvdata(dev);
- unsigned int timeout = TALITOS_TIMEOUT;
-
- setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR);
- while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO)
- & TALITOS_RNGUSR_LO_RD)
- && --timeout)
- cpu_relax();
- if (timeout == 0) {
- dev_err(dev, "failed to reset rng hw\n");
- return -ENODEV;
- }
-
- /* start generating */
- setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0);
-
- return 0;
-}
-
-static int talitos_register_rng(struct device *dev)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
- int err;
-
- priv->rng.name = dev_driver_string(dev);
- priv->rng.init = talitos_rng_init;
- priv->rng.data_present = talitos_rng_data_present;
- priv->rng.data_read = talitos_rng_data_read;
- priv->rng.priv = (unsigned long)dev;
-
- err = hwrng_register(&priv->rng);
- if (!err)
- priv->rng_registered = true;
-
- return err;
-}
-
-static void talitos_unregister_rng(struct device *dev)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
-
- if (!priv->rng_registered)
- return;
-
- hwrng_unregister(&priv->rng);
- priv->rng_registered = false;
-}
/*
* crypto alg
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 56e36a65ddcc..fa8c71b1f90f 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -431,3 +431,8 @@ static inline bool has_ftr_sec1(struct talitos_private *priv)
#define DESC_PTR_LNKTBL_JUMP 0x80
#define DESC_PTR_LNKTBL_RET 0x02
#define DESC_PTR_LNKTBL_NEXT 0x01
+
+/* Hardware RNG */
+
+int talitos_register_rng(struct device *dev);
+void talitos_unregister_rng(struct device *dev);
--
2.54.0
^ permalink raw reply related
* [PATCH v2 02/19] crypto: talitos - Move driver into dedicated directory
From: Paul Louvel @ 2026-06-11 7:35 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
Move the talitos driver files from drivers/crypto/ into
drivers/crypto/talitos/ to accommodate upcoming code
reorganization.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/Kconfig | 38 +---------------------------------
drivers/crypto/Makefile | 2 +-
drivers/crypto/talitos/Kconfig | 36 ++++++++++++++++++++++++++++++++
drivers/crypto/talitos/Makefile | 1 +
drivers/crypto/{ => talitos}/talitos.c | 0
drivers/crypto/{ => talitos}/talitos.h | 0
6 files changed, 39 insertions(+), 38 deletions(-)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index d23b58b81ca3..783b5dc42a42 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -253,43 +253,7 @@ config CRYPTO_DEV_HIFN_795X_RNG
on the HIFN 795x crypto adapters.
source "drivers/crypto/caam/Kconfig"
-
-config CRYPTO_DEV_TALITOS
- tristate "Talitos Freescale Security Engine (SEC)"
- select CRYPTO_AEAD
- select CRYPTO_AUTHENC
- select CRYPTO_SKCIPHER
- select CRYPTO_HASH
- select CRYPTO_LIB_DES
- select HW_RANDOM
- depends on FSL_SOC
- help
- Say 'Y' here to use the Freescale Security Engine (SEC)
- to offload cryptographic algorithm computation.
-
- The Freescale SEC is present on PowerQUICC 'E' processors, such
- as the MPC8349E and MPC8548E.
-
- To compile this driver as a module, choose M here: the module
- will be called talitos.
-
-config CRYPTO_DEV_TALITOS1
- bool "SEC1 (SEC 1.0 and SEC Lite 1.2)"
- depends on CRYPTO_DEV_TALITOS
- depends on PPC_8xx || PPC_82xx
- default y
- help
- Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0
- found on MPC82xx or the Freescale Security Engine (SEC Lite)
- version 1.2 found on MPC8xx
-
-config CRYPTO_DEV_TALITOS2
- bool "SEC2+ (SEC version 2.0 or upper)"
- depends on CRYPTO_DEV_TALITOS
- default y if !PPC_8xx
- help
- Say 'Y' here to use the Freescale Security Engine (SEC)
- version 2 and following as found on MPC83xx, MPC85xx, etc ...
+source "drivers/crypto/talitos/Kconfig"
config CRYPTO_DEV_PPC4XX
tristate "Driver AMCC PPC4xx crypto accelerator"
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 283bbc650b5b..a059139d4a75 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -35,7 +35,7 @@ obj-$(CONFIG_CRYPTO_DEV_SA2UL) += sa2ul.o
obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
obj-$(CONFIG_CRYPTO_DEV_SL3516) += gemini/
obj-y += stm32/
-obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
+obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos/
obj-$(CONFIG_CRYPTO_DEV_TEGRA) += tegra/
obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
diff --git a/drivers/crypto/talitos/Kconfig b/drivers/crypto/talitos/Kconfig
new file mode 100644
index 000000000000..c3470553a966
--- /dev/null
+++ b/drivers/crypto/talitos/Kconfig
@@ -0,0 +1,36 @@
+config CRYPTO_DEV_TALITOS
+ tristate "Talitos Freescale Security Engine (SEC)"
+ select CRYPTO_AEAD
+ select CRYPTO_AUTHENC
+ select CRYPTO_SKCIPHER
+ select CRYPTO_HASH
+ select CRYPTO_LIB_DES
+ select HW_RANDOM
+ depends on FSL_SOC
+ help
+ Say 'Y' here to use the Freescale Security Engine (SEC)
+ to offload cryptographic algorithm computation.
+
+ The Freescale SEC is present on PowerQUICC 'E' processors, such
+ as the MPC8349E and MPC8548E.
+
+ To compile this driver as a module, choose M here: the module
+ will be called talitos.
+
+config CRYPTO_DEV_TALITOS1
+ bool "SEC1 (SEC 1.0 and SEC Lite 1.2)"
+ depends on CRYPTO_DEV_TALITOS
+ depends on PPC_8xx || PPC_82xx
+ default y
+ help
+ Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0
+ found on MPC82xx or the Freescale Security Engine (SEC Lite)
+ version 1.2 found on MPC8xx
+
+config CRYPTO_DEV_TALITOS2
+ bool "SEC2+ (SEC version 2.0 or upper)"
+ depends on CRYPTO_DEV_TALITOS
+ default y if !PPC_8xx
+ help
+ Say 'Y' here to use the Freescale Security Engine (SEC)
+ version 2 and following as found on MPC83xx, MPC85xx, etc ...
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
new file mode 100644
index 000000000000..fcc5db5e63c2
--- /dev/null
+++ b/drivers/crypto/talitos/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos/talitos.c
similarity index 100%
rename from drivers/crypto/talitos.c
rename to drivers/crypto/talitos/talitos.c
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos/talitos.h
similarity index 100%
rename from drivers/crypto/talitos.h
rename to drivers/crypto/talitos/talitos.h
--
2.54.0
^ permalink raw reply related
* [PATCH v2 01/19] crypto: talitos/hash - Use CRYPTO_AHASH_BLOCK_ONLY API
From: Paul Louvel @ 2026-06-11 7:35 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
In-Reply-To: <20260611-7-1-rc1_talitos_cleanup-v2-0-aa4a813ce69b@bootlin.com>
The hash implementation maintained a software buffer to accumulate
partial blocks across update() calls, copying data to/from scatterlists
with sg_copy_to_buffer()/sg_pcopy_to_buffer() and chaining in a virtual
scatterlist entry. This is unnecessary now with
CRYPTO_AHASH_ALG_BLOCK_ONLY flag.
Remove unnecessary fields in the request and export structure. On
completion, pass any remaining tail bytes back via
ahash_request_complete() so that the core re-submits them with the next
request.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos.c | 151 ++++++++++++++++++-----------------------------
1 file changed, 57 insertions(+), 94 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 584508963241..12fb61ee8066 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -935,31 +935,23 @@ struct talitos_ctx {
unsigned int authkeylen;
};
-#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
struct talitos_ahash_req_ctx {
u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
unsigned int hw_context_size;
- u8 buf[2][HASH_MAX_BLOCK_SIZE];
- int buf_idx;
unsigned int swinit;
unsigned int first_request;
unsigned int last_request;
unsigned int to_hash_later;
- unsigned int nbuf;
- struct scatterlist bufsl[2];
- struct scatterlist *psrc;
};
struct talitos_export_state {
u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
- u8 buf[HASH_MAX_BLOCK_SIZE];
unsigned int swinit;
unsigned int first_request;
unsigned int last_request;
unsigned int to_hash_later;
- unsigned int nbuf;
};
static int aead_setkey(struct crypto_aead *authenc,
@@ -1826,14 +1818,8 @@ static void ahash_done(struct device *dev,
struct talitos_edesc *next;
if (is_sec1) {
- if (!req_ctx->last_request && req_ctx->to_hash_later) {
- /* Position any partial block for next update/final/finup */
- req_ctx->buf_idx = (req_ctx->buf_idx + 1) & 1;
- req_ctx->nbuf = req_ctx->to_hash_later;
- }
-
free_edesc_list_from(areq, edesc);
- ahash_request_complete(areq, err);
+ ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
} else {
next = edesc->next_desc;
@@ -1851,14 +1837,9 @@ static void ahash_done(struct device *dev,
return;
}
out:
- if (!req_ctx->last_request && req_ctx->to_hash_later) {
- /* Position any partial block for next update/final/finup */
- req_ctx->buf_idx = (req_ctx->buf_idx + 1) & 1;
- req_ctx->nbuf = req_ctx->to_hash_later;
- }
if (err && next)
free_edesc_list_from(areq, next);
- ahash_request_complete(areq, err);
+ ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
}
}
@@ -1978,7 +1959,7 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
size_t offset = 0;
do {
- src = scatterwalk_ffwd(tmp, req_ctx->psrc, offset);
+ src = scatterwalk_ffwd(tmp, areq->src, offset);
to_hash_this_desc =
min(nbytes, ALIGN_DOWN(desc_max, blocksize));
@@ -1991,8 +1972,7 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
return edesc;
}
- edesc->src =
- scatterwalk_ffwd(edesc->bufsl, req_ctx->psrc, offset);
+ edesc->src = scatterwalk_ffwd(edesc->bufsl, areq->src, offset);
edesc->desc.hdr = ctx->desc_hdr_template;
edesc->first = offset == 0;
edesc->last = nbytes - to_hash_this_desc == 0;
@@ -2045,62 +2025,17 @@ static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
bool is_sec1 = has_ftr_sec1(dev_get_drvdata(ctx->dev));
unsigned int nbytes_to_hash;
unsigned int to_hash_later;
- unsigned int nsg;
- int nents;
struct device *dev = ctx->dev;
- u8 *ctx_buf = req_ctx->buf[req_ctx->buf_idx];
int ret;
- if (!req_ctx->last_request && (nbytes + req_ctx->nbuf <= blocksize)) {
- /* Buffer up to one whole block */
- nents = sg_nents_for_len(areq->src, nbytes);
- if (nents < 0) {
- dev_err(dev, "Invalid number of src SG.\n");
- return nents;
- }
- sg_copy_to_buffer(areq->src, nents,
- ctx_buf + req_ctx->nbuf, nbytes);
- req_ctx->nbuf += nbytes;
- return 0;
- }
-
- /* At least (blocksize + 1) bytes are available to hash */
- nbytes_to_hash = nbytes + req_ctx->nbuf;
- to_hash_later = nbytes_to_hash & (blocksize - 1);
+ nbytes_to_hash = ALIGN_DOWN(nbytes, blocksize);
+ to_hash_later = nbytes - nbytes_to_hash;
- if (req_ctx->last_request)
+ if (req_ctx->last_request) {
+ nbytes_to_hash = nbytes;
to_hash_later = 0;
- else if (to_hash_later)
- /* There is a partial block. Hash the full block(s) now */
- nbytes_to_hash -= to_hash_later;
- else {
- /* Keep one block buffered */
- nbytes_to_hash -= blocksize;
- to_hash_later = blocksize;
- }
-
- /* Chain in any previously buffered data */
- if (req_ctx->nbuf) {
- nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
- sg_init_table(req_ctx->bufsl, nsg);
- sg_set_buf(req_ctx->bufsl, ctx_buf, req_ctx->nbuf);
- if (nsg > 1)
- sg_chain(req_ctx->bufsl, 2, areq->src);
- req_ctx->psrc = req_ctx->bufsl;
- } else
- req_ctx->psrc = areq->src;
-
- if (to_hash_later) {
- nents = sg_nents_for_len(areq->src, nbytes);
- if (nents < 0) {
- dev_err(dev, "Invalid number of src SG.\n");
- return nents;
- }
- sg_pcopy_to_buffer(areq->src, nents,
- req_ctx->buf[(req_ctx->buf_idx + 1) & 1],
- to_hash_later,
- nbytes - to_hash_later);
}
+
req_ctx->to_hash_later = to_hash_later;
edesc = ahash_process_req_prepare(areq, nbytes_to_hash, blocksize,
@@ -2125,8 +2060,6 @@ static int ahash_init(struct ahash_request *areq)
dma_addr_t dma;
/* Initialize the context */
- req_ctx->buf_idx = 0;
- req_ctx->nbuf = 0;
req_ctx->first_request = 1;
req_ctx->swinit = 0; /* assume h/w init of context */
size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
@@ -2223,12 +2156,10 @@ static int ahash_export(struct ahash_request *areq, void *out)
memcpy(export->hw_context, req_ctx->hw_context,
req_ctx->hw_context_size);
- memcpy(export->buf, req_ctx->buf[req_ctx->buf_idx], req_ctx->nbuf);
export->swinit = req_ctx->swinit;
export->first_request = req_ctx->first_request;
export->last_request = req_ctx->last_request;
export->to_hash_later = req_ctx->to_hash_later;
- export->nbuf = req_ctx->nbuf;
return 0;
}
@@ -2249,12 +2180,10 @@ static int ahash_import(struct ahash_request *areq, const void *in)
: TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
req_ctx->hw_context_size = size;
memcpy(req_ctx->hw_context, export->hw_context, size);
- memcpy(req_ctx->buf[0], export->buf, export->nbuf);
req_ctx->swinit = export->swinit;
req_ctx->first_request = export->first_request;
req_ctx->last_request = export->last_request;
req_ctx->to_hash_later = export->to_hash_later;
- req_ctx->nbuf = export->nbuf;
dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
DMA_TO_DEVICE);
@@ -2932,8 +2861,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "md5",
.cra_driver_name = "md5-talitos",
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -2948,8 +2880,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "sha1",
.cra_driver_name = "sha1-talitos",
.cra_blocksize = SHA1_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -2964,8 +2899,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "sha224",
.cra_driver_name = "sha224-talitos",
.cra_blocksize = SHA224_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -2980,8 +2918,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "sha256",
.cra_driver_name = "sha256-talitos",
.cra_blocksize = SHA256_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -2996,8 +2937,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "sha384",
.cra_driver_name = "sha384-talitos",
.cra_blocksize = SHA384_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3012,8 +2956,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "sha512",
.cra_driver_name = "sha512-talitos",
.cra_blocksize = SHA512_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3028,8 +2975,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(md5)",
.cra_driver_name = "hmac-md5-talitos",
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3044,8 +2994,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(sha1)",
.cra_driver_name = "hmac-sha1-talitos",
.cra_blocksize = SHA1_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3060,8 +3013,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(sha224)",
.cra_driver_name = "hmac-sha224-talitos",
.cra_blocksize = SHA224_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3076,8 +3032,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(sha256)",
.cra_driver_name = "hmac-sha256-talitos",
.cra_blocksize = SHA256_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3092,8 +3051,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(sha384)",
.cra_driver_name = "hmac-sha384-talitos",
.cra_blocksize = SHA384_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3108,8 +3070,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(sha512)",
.cra_driver_name = "hmac-sha512-talitos",
.cra_blocksize = SHA512_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3181,8 +3146,6 @@ static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
algt.alg.hash);
ctx->keylen = 0;
- crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
- sizeof(struct talitos_ahash_req_ctx));
return talitos_init_common(ctx, talitos_alg);
}
--
2.54.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox