Linux cryptographic layer development
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From: sashiko-bot@kernel.org
To: "Kuldeep Singh" <kuldeep.singh@oss.qualcomm.com>,
	"Bartosz Golaszewski" <brgl@kernel.org>,
	"Herbert Xu" <herbert@gondor.apana.org.au>,
	"David S. Miller" <davem@davemloft.net>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Konrad Dybcio" <konradybcio@kernel.org>,
	"Abel Vesa" <abelvesa@kernel.org>
Cc: "Bartosz Golaszewski" <bartosz.golaszewski@oss.qualcomm.com>,
	linux-crypto@vger.kernel.org, devicetree@vger.kernel.org,
	"Konrad Dybcio" <konrad.dybcio@oss.qualcomm.com>,
	"Wenjia Zhang" <wenjia.zhang@oss.qualcomm.com>
Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: shikra: Correct QCE node configuration
Date: Thu, 12 Nov 2026 13:16:03 +0000	[thread overview]
Message-ID: <sashiko-outbox-211156@kernel.org> (raw)
In-Reply-To: <20261112-shikra_qce_fix-v2-2-2ce112cc2ccf@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] arm64: dts: qcom: shikra: unexplained removal of QCE memory
  interconnect
--

commit accab4d6610b99099fcb37c8fbe0de4933119ef7
Author: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>

arm64: dts: qcom: shikra: Correct QCE node configuration

This commit updates the fallback compatible string and replaces the memory
interconnect properties with the core clock in the Shikra QCE device tree
node.

> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index 0a95ad5a5582c..d5f0ef863173e 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
> @@ -1208,7 +1208,7 @@ cryptobam: dma-controller@1b04000 {
>  		};
>  
>  		crypto: crypto@1b3a000 {
> -			compatible = "qcom,shikra-qce", "qcom,sm8150-qce", "qcom,qce";
> +			compatible = "qcom,shikra-qce", "qcom,ipq4019-qce", "qcom,qce";
>  			reg = <0x0 0x01b3a000 0x0 0x6000>;
>  			dmas = <&cryptobam 4>, <&cryptobam 5>;
>  			dma-names = "rx", "tx";
> @@ -1219,9 +1219,8 @@ crypto: crypto@1b3a000 {
>  				 <&apps_smmu 0x96 0x0011>,
>  				 <&apps_smmu 0x98 0x0001>,
>  				 <&apps_smmu 0x9f 0x0>;
> -			interconnects = <&system_noc MASTER_CRYPTO_CORE0 0
> -					 &mc_virt SLAVE_EBI_CH0 0>;
> -			interconnect-names = "memory";
> +			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
> +			clock-names = "core";
>  		};

[Severity: Medium]
Was the removal of interconnects and interconnect-names intentional here?

qce_crypto_probe() acquires both the core clock (qce->core) and the "memory"
interconnect path (qce->mem_path), and qce_runtime_resume() votes for
QCE_DEFAULT_MEM_BANDWIDTH on qce->mem_path alongside enabling qce->core.
Without the interconnect properties, the QCE driver no longer scales the
MASTER_CRYPTO_CORE0 to SLAVE_EBI_CH0 path during crypto transfers, and the
commit message does not mention removing it.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-shikra_qce_fix-v2-0-2ce112cc2ccf@oss.qualcomm.com?part=2

      reply	other threads:[~2026-11-12 13:16 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-12 12:51 [PATCH v2 0/2] Shikra: Fix qce configuration Kuldeep Singh
2026-11-12 12:51 ` [PATCH v2 1/2] dt-bindings: crypto: Correct Shikra QCE compatible hierarchy Kuldeep Singh
2026-11-12 12:51 ` [PATCH v2 2/2] arm64: dts: qcom: shikra: Correct QCE node configuration Kuldeep Singh
2026-11-12 13:16   ` sashiko-bot [this message]

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