From: Zhen Lei <thunder.leizhen@huawei.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Guo Ren <guoren@kernel.org>,
devicetree <devicetree@vger.kernel.org>,
linux-csky <linux-csky@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>
Cc: Zhen Lei <thunder.leizhen@huawei.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Haoyu Lv <lvhaoyu@huawei.com>, Libin <huawei.libin@huawei.com>,
Kefeng Wang <wangkefeng.wang@huawei.com>,
"Jianguo Chen" <chenjianguo3@huawei.com>
Subject: [PATCH v4 4/4] dt-bindings: dw-apb-ictl: support hierarchy irq domain
Date: Tue, 15 Sep 2020 16:43:05 +0800 [thread overview]
Message-ID: <20200915084305.3085-5-thunder.leizhen@huawei.com> (raw)
In-Reply-To: <20200915084305.3085-1-thunder.leizhen@huawei.com>
Add support to use dw-apb-ictl as primary interrupt controller.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
.../bindings/interrupt-controller/snps,dw-apb-ictl.txt | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
index 086ff08322db94f..2db59df9408f4c6 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
@@ -2,7 +2,8 @@ Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
Synopsys DesignWare provides interrupt controller IP for APB known as
dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
-APB bus, e.g. Marvell Armada 1500.
+APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
+controller in some SoCs, e.g. Hisilicon SD5203.
Required properties:
- compatible: shall be "snps,dw-apb-ictl"
@@ -10,6 +11,8 @@ Required properties:
region starting with ENABLE_LOW register
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
+
+Additional required property when it's used as secondary interrupt controller:
- interrupts: interrupt reference to primary interrupt controller
The interrupt sources map to the corresponding bits in the interrupt
@@ -21,6 +24,7 @@ registers, i.e.
- (optional) fast interrupts start at 64.
Example:
+ /* dw_apb_ictl is used as secondary interrupt controller */
aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
@@ -29,3 +33,11 @@ Example:
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ /* dw_apb_ictl is used as primary interrupt controller */
+ vic: interrupt-controller@10130000 {
+ compatible = "snps,dw-apb-ictl";
+ reg = <0x10130000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
--
1.8.3
prev parent reply other threads:[~2020-09-15 8:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-15 8:43 [PATCH v4 0/4] irqchip: dw-apb-ictl: support hierarchy irq domain Zhen Lei
2020-09-15 8:43 ` [PATCH v4 1/4] genirq: define an empty function set_handle_irq() if !GENERIC_IRQ_MULTI_HANDLER Zhen Lei
2020-09-17 3:46 ` Leizhen (ThunderTown)
2020-09-17 9:32 ` Marc Zyngier
2020-09-17 9:47 ` Leizhen (ThunderTown)
2020-09-15 8:43 ` [PATCH v4 2/4] irqchip: dw-apb-ictl: prepare for support hierarchy irq domain Zhen Lei
2020-09-15 8:43 ` [PATCH v4 3/4] irqchip: dw-apb-ictl: " Zhen Lei
2020-09-15 8:43 ` Zhen Lei [this message]
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