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Tue, 24 Nov 2020 14:29:09 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 8F862307005; Tue, 24 Nov 2020 15:29:05 +0100 (CET) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 75D6620222D7E; Tue, 24 Nov 2020 15:29:05 +0100 (CET) Date: Tue, 24 Nov 2020 15:29:05 +0100 From: Peter Zijlstra To: guoren@kernel.org Cc: arnd@arndb.de, palmerdabbelt@google.com, paul.walmsley@sifive.com, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org, Guo Ren , Michael Clark Subject: Re: [PATCH 1/5] riscv: Coding convention for xchg Message-ID: <20201124142905.GH2414@hirez.programming.kicks-ass.net> References: <1606225437-22948-1-git-send-email-guoren@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1606225437-22948-1-git-send-email-guoren@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-csky@vger.kernel.org On Tue, Nov 24, 2020 at 01:43:53PM +0000, guoren@kernel.org wrote: > From: Guo Ren > > This is prepare for QUEUED_SPINLOCKS which need xchg support short > type value. > - Remove unused codes (xchg32, xchg64, cmpxchg32 ...) > - Combine xchg_relaxed, xchg_acquire, xchg_release into one asm > - Make atomic.aq/rl with seperated fence acquire & release Every time you find yourself doing multiple things, make it multiple patches. > @@ -242,58 +239,58 @@ static __always_inline s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u > * atomic_{cmp,}xchg is required to have exactly the same ordering semantics as > * {cmp,}xchg and the operations that return, so they need a full barrier. > */ > +#define ATOMIC_OP(c_t, prefix) \ > static __always_inline \ > c_t atomic##prefix##_xchg_relaxed(atomic##prefix##_t *v, c_t n) \ > { \ > + return xchg_relaxed(&(v->counter), n); \ > } \ > static __always_inline \ > c_t atomic##prefix##_xchg_acquire(atomic##prefix##_t *v, c_t n) \ > { \ > + return xchg_acquire(&(v->counter), n); \ > } \ > static __always_inline \ > c_t atomic##prefix##_xchg_release(atomic##prefix##_t *v, c_t n) \ > { \ > + return xchg_release(&(v->counter), n); \ > } \ > static __always_inline \ > c_t atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \ > { \ > + return xchg(&(v->counter), n); \ > } \ > static __always_inline \ > c_t atomic##prefix##_cmpxchg_relaxed(atomic##prefix##_t *v, \ > c_t o, c_t n) \ > { \ > + return cmpxchg_relaxed(&(v->counter), o, n); \ > } \ > static __always_inline \ > c_t atomic##prefix##_cmpxchg_acquire(atomic##prefix##_t *v, \ > c_t o, c_t n) \ > { \ > + return cmpxchg_acquire(&(v->counter), o, n); \ > } \ > static __always_inline \ > c_t atomic##prefix##_cmpxchg_release(atomic##prefix##_t *v, \ > c_t o, c_t n) \ > { \ > + return cmpxchg_release(&(v->counter), o, n); \ > } \ > static __always_inline \ > c_t atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \ > { \ > + return cmpxchg(&(v->counter), o, n); \ > } > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > index 262e5bb..5609185 100644 > --- a/arch/riscv/include/asm/cmpxchg.h > +++ b/arch/riscv/include/asm/cmpxchg.h > @@ -44,118 +44,31 @@ > _x_, sizeof(*(ptr))); \ > }) > > #define xchg_acquire(ptr, x) \ > ({ \ > + __typeof__(*(ptr)) _x_ = (x); \ > + __ret = __xchg_relaxed((ptr), _x_, sizeof(*(ptr))); \ > + __acquire_fence(); \ > __ret; \ > }) > > #define xchg_release(ptr, x) \ > ({ \ > __typeof__(*(ptr)) _x_ = (x); \ > + __release_fence(); \ > + (__typeof__(*(ptr))) __xchg_relaxed((ptr), \ > _x_, sizeof(*(ptr))); \ > }) > > #define xchg(ptr, x) \ > ({ \ > + __typeof__(*(ptr)) __ret; \ > __typeof__(*(ptr)) _x_ = (x); \ > + __smp_mb(); \ > + __ret = __xchg_relaxed((ptr), _x_, sizeof(*(ptr))); \ > + __smp_mb(); \ > + __ret; \ > }) > > /* Why are you defining *{,_acquire,_release}() at all, doesn't atomic-fallback.h DTRT for you?