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Tue, 24 Nov 2020 14:39:33 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id EFED53012DF; Tue, 24 Nov 2020 15:39:31 +0100 (CET) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id D902820222D65; Tue, 24 Nov 2020 15:39:31 +0100 (CET) Date: Tue, 24 Nov 2020 15:39:31 +0100 From: Peter Zijlstra To: guoren@kernel.org Cc: arnd@arndb.de, palmerdabbelt@google.com, paul.walmsley@sifive.com, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org, Guo Ren , Michael Clark Subject: Re: [PATCH 2/5] riscv: Add QUEUED_SPINLOCKS & QUEUED_RWLOCKS supported Message-ID: <20201124143931.GI2414@hirez.programming.kicks-ass.net> References: <1606225437-22948-1-git-send-email-guoren@kernel.org> <1606225437-22948-2-git-send-email-guoren@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1606225437-22948-2-git-send-email-guoren@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-csky@vger.kernel.org On Tue, Nov 24, 2020 at 01:43:54PM +0000, guoren@kernel.org wrote: > diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild > index 59dd7be..6f5f438 100644 > --- a/arch/riscv/include/asm/Kbuild > +++ b/arch/riscv/include/asm/Kbuild > @@ -6,3 +6,6 @@ generic-y += kvm_para.h > generic-y += local64.h > generic-y += user.h > generic-y += vmlinux.lds.h > +generic-y += mcs_spinlock.h > +generic-y += qrwlock.h > +generic-y += qspinlock.h > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > index 5609185..e178700 100644 > --- a/arch/riscv/include/asm/cmpxchg.h > +++ b/arch/riscv/include/asm/cmpxchg.h > @@ -16,7 +16,43 @@ > __typeof__(ptr) __ptr = (ptr); \ > __typeof__(new) __new = (new); \ > __typeof__(*(ptr)) __ret; \ > + register unsigned long __rc, tmp, align, addr; \ > switch (size) { \ > + case 2: \ > + align = ((unsigned long) __ptr & 0x3); \ > + addr = ((unsigned long) __ptr & ~0x3); \ > + if (align) { \ > + __asm__ __volatile__ ( \ > + "0: lr.w %0, 0(%z4)\n" \ > + " move %1, %0\n" \ > + " slli %1, %1, 16\n" \ > + " srli %1, %1, 16\n" \ > + " move %2, %z3\n" \ > + " slli %2, %2, 16\n" \ > + " or %1, %2, %1\n" \ > + " sc.w %2, %1, 0(%z4)\n" \ > + " bnez %2, 0b\n" \ > + " srli %0, %0, 16\n" \ > + : "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \ > + : "rJ" (__new), "rJ"(addr) \ > + : "memory"); \ > + } else { \ > + __asm__ __volatile__ ( \ > + "0: lr.w %0, (%z4)\n" \ > + " move %1, %0\n" \ > + " srli %1, %1, 16\n" \ > + " slli %1, %1, 16\n" \ > + " move %2, %z3\n" \ > + " or %1, %2, %1\n" \ > + " sc.w %2, %1, 0(%z4)\n" \ > + " bnez %2, 0b\n" \ > + " slli %0, %0, 16\n" \ > + " srli %0, %0, 16\n" \ > + : "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \ > + : "rJ" (__new), "rJ"(addr) \ > + : "memory"); \ > + } \ > + break; \ > case 4: \ > __asm__ __volatile__ ( \ > " amoswap.w %0, %2, %1\n" \ I'm pretty sure there's a handfull of implementations like this out there... if only we could share. Anyway, this too should be an independent patch.