From: Peter Zijlstra <peterz@infradead.org>
To: guoren@kernel.org
Cc: arnd@arndb.de, linux-kernel@vger.kernel.org,
linux-csky@vger.kernel.org, linux-arch@vger.kernel.org,
Guo Ren <guoren@linux.alibaba.com>,
"Paul E . McKenney" <paulmck@kernel.org>
Subject: Re: [PATCH v2 4/5] csky: Fixup asm/cmpxchg.h with correct ordering barrier
Date: Thu, 7 Jan 2021 13:40:55 +0100 [thread overview]
Message-ID: <X/cBV8Bll0K2PwTx@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1608478763-60148-4-git-send-email-guoren@kernel.org>
On Sun, Dec 20, 2020 at 03:39:22PM +0000, guoren@kernel.org wrote:
> +#define cmpxchg(ptr, o, n) \
> +({ \
> + __typeof__(*(ptr)) __ret; \
> + __smp_release_fence(); \
> + __ret = cmpxchg_relaxed(ptr, o, n); \
> + __smp_acquire_fence(); \
> + __ret; \
> +})
So you failed to Cc me on patch #2 that introduces these barriers. I've
dug it out, but I'm still terribly confused on all that.
On first reading the above looks wrong.
Could you also clarify the difference (if any) between your bar.brwarw
and sync instruction?
Specifically, about transitiviry, or whatever we seem to be calling that
today.
next prev parent reply other threads:[~2021-01-07 12:42 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-20 15:39 [PATCH v2 1/5] csky: Remove custom asm/atomic.h implementation guoren
2020-12-20 15:39 ` [PATCH v2 2/5] csky: Fixup barrier design guoren
2020-12-20 15:39 ` [PATCH v2 3/5] csky: Fixup futex SMP implementation guoren
2020-12-20 15:39 ` [PATCH v2 4/5] csky: Fixup asm/cmpxchg.h with correct ordering barrier guoren
2021-01-07 12:40 ` Peter Zijlstra [this message]
2021-01-21 7:05 ` Guo Ren
2020-12-20 15:39 ` [PATCH v2 5/5] csky: Cleanup asm/spinlock.h guoren
2021-01-07 12:45 ` Peter Zijlstra
2021-01-07 11:19 ` [PATCH v2 1/5] csky: Remove custom asm/atomic.h implementation Peter Zijlstra
2021-01-21 7:10 ` Guo Ren
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