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Thu, 14 Sep 2023 23:23:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEnXl+iWXUNkjlGJTgGvcCE0+QSxnHePkAelhd7hHtYCVfy9sGfEJ3pO9ERuYXBQlky5+8lHw== X-Received: by 2002:a05:6808:15a4:b0:3a1:e12b:2f80 with SMTP id t36-20020a05680815a400b003a1e12b2f80mr1008543oiw.35.1694758995419; Thu, 14 Sep 2023 23:23:15 -0700 (PDT) Received: from redhat.com ([2804:1b3:a803:4ff9:7c29:fe41:6aa7:43df]) by smtp.gmail.com with ESMTPSA id e2-20020a9d7302000000b006c0d686f76esm1338510otk.63.2023.09.14.23.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 23:23:14 -0700 (PDT) Date: Fri, 15 Sep 2023 03:23:05 -0300 From: Leonardo Bras To: guoren@kernel.org Cc: paul.walmsley@sifive.com, anup@brainfault.org, peterz@infradead.org, mingo@redhat.com, will@kernel.org, palmer@rivosinc.com, longman@redhat.com, boqun.feng@gmail.com, tglx@linutronix.de, paulmck@kernel.org, rostedt@goodmis.org, rdunlap@infradead.org, catalin.marinas@arm.com, conor.dooley@microchip.com, xiaoguang.xing@sophgo.com, bjorn@rivosinc.com, alexghiti@rivosinc.com, keescook@chromium.org, greentime.hu@sifive.com, ajones@ventanamicro.com, jszhang@kernel.org, wefu@redhat.com, wuwei2016@iscas.ac.cn, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, virtualization@lists.linux-foundation.org, linux-csky@vger.kernel.org, Guo Ren Subject: Re: [PATCH V11 13/17] RISC-V: paravirt: pvqspinlock: Add SBI implementation Message-ID: References: <20230910082911.3378782-1-guoren@kernel.org> <20230910082911.3378782-14-guoren@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230910082911.3378782-14-guoren@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-csky@vger.kernel.org On Sun, Sep 10, 2023 at 04:29:07AM -0400, guoren@kernel.org wrote: > From: Guo Ren > > Implement pv_kick with SBI implementation, and add SBI_EXT_PVLOCK > extension detection. > > Signed-off-by: Guo Ren > Signed-off-by: Guo Ren > --- > arch/riscv/include/asm/sbi.h | 6 ++++++ > arch/riscv/kernel/qspinlock_paravirt.c | 7 ++++++- > 2 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index e0233b3d7a5f..3533f8d4f3e2 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -30,6 +30,7 @@ enum sbi_ext_id { > SBI_EXT_HSM = 0x48534D, > SBI_EXT_SRST = 0x53525354, > SBI_EXT_PMU = 0x504D55, > + SBI_EXT_PVLOCK = 0xAB0401, > > /* Experimentals extensions must lie within this range */ > SBI_EXT_EXPERIMENTAL_START = 0x08000000, > @@ -243,6 +244,11 @@ enum sbi_pmu_ctr_type { > /* Flags defined for counter stop function */ > #define SBI_PMU_STOP_FLAG_RESET (1 << 0) > > +/* SBI PVLOCK (kick cpu out of wfi) */ > +enum sbi_ext_pvlock_fid { > + SBI_EXT_PVLOCK_KICK_CPU = 0, > +}; > + > #define SBI_SPEC_VERSION_DEFAULT 0x1 > #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 > #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f > diff --git a/arch/riscv/kernel/qspinlock_paravirt.c b/arch/riscv/kernel/qspinlock_paravirt.c > index a0ad4657f437..571626f350be 100644 > --- a/arch/riscv/kernel/qspinlock_paravirt.c > +++ b/arch/riscv/kernel/qspinlock_paravirt.c > @@ -11,6 +11,8 @@ > > void pv_kick(int cpu) > { > + sbi_ecall(SBI_EXT_PVLOCK, SBI_EXT_PVLOCK_KICK_CPU, > + cpuid_to_hartid_map(cpu), 0, 0, 0, 0, 0); > return; > } > > @@ -25,7 +27,7 @@ void pv_wait(u8 *ptr, u8 val) > if (READ_ONCE(*ptr) != val) > goto out; > > - /* wait_for_interrupt(); */ > + wait_for_interrupt(); > out: > local_irq_restore(flags); > } > @@ -62,6 +64,9 @@ void __init pv_qspinlock_init(void) > if(sbi_get_firmware_id() != SBI_EXT_BASE_IMPL_ID_KVM) > return; > > + if (!sbi_probe_extension(SBI_EXT_PVLOCK)) > + return; > + > pr_info("PV qspinlocks enabled\n"); > __pv_init_lock_hash(); > > -- > 2.36.1 > IIUC this PVLOCK extension is now a requirement to use pv_qspinlock(), and it allows a cpu to use an instruction to wait for interrupt in pv_wait(), and kicks it out of this wait using a new sbi_ecall() on pv_kick(). Overall it LGTM, but would be nice to have the reference doc in the commit msg. I end up inferring some of the inner workings by your implementation, which is not ideal for reviewing. If understanding above is right, Reviewed-by: Leonardo Bras Thanks! Leo