From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 571FCC74A5B for ; Wed, 29 Mar 2023 17:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229436AbjC2Rkz (ORCPT ); Wed, 29 Mar 2023 13:40:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229456AbjC2Rky (ORCPT ); Wed, 29 Mar 2023 13:40:54 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECB674ED9 for ; Wed, 29 Mar 2023 10:40:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680111651; x=1711647651; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=Fiw5JCqqzRwHC/tpXvzLldBOZGc6L3O9xT9eZB/dtGQ=; b=n5bo2uTj3FTGyvSZT5V1r2DMp3+Sg2uQI+MK/26n4M4n1s64IafSbW1M bdNLStt8XLI2aH6+lX4j0JUThPpYQ4aaYYvPaAqU2IVOSh9iZ/ymOMr03 SdT3u7BAONUna+rp0slaGscTPBZZ4ZfDv32ULxx9QSsN6n2pEMHsj3ljG XumXTGN1pDOPAV2W8VS8CIq0RWZq3Q+8YmG7JMvaID60LBXmFSVnJvo0X MssGcX5wHy7yie23zKQlYt/xKpI7HGtMQ65UZKth3Y+gFFfFPNpsHJor9 5aMo3VVlcrVp2sfnvxwc5GuudBffPVxIus0AcT9X+6VpXjfOVnETTx5ON Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10664"; a="368725664" X-IronPort-AV: E=Sophos;i="5.98,301,1673942400"; d="scan'208";a="368725664" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2023 10:40:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10664"; a="753688784" X-IronPort-AV: E=Sophos;i="5.98,301,1673942400"; d="scan'208";a="753688784" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [10.212.109.34]) ([10.212.109.34]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2023 10:40:30 -0700 Message-ID: <07c64a6b-57dd-a63d-ef05-276774a43996@intel.com> Date: Wed, 29 Mar 2023 10:40:30 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.9.0 Subject: Re: [PATCH] cxl/region: Move coherence tracking into cxl_region_attach() Content-Language: en-US To: Dan Williams , linux-cxl@vger.kernel.org Cc: vishal.l.verma@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com References: <168002858817.50647.1217607907088920888.stgit@dwillia2-xfh.jf.intel.com> From: Dave Jiang In-Reply-To: <168002858817.50647.1217607907088920888.stgit@dwillia2-xfh.jf.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org On 3/28/23 11:36 AM, Dan Williams wrote: > Each time the contents of a given HPA are potentially changed in a cache > incoherent manner the CXL core sets CXL_REGION_F_INCOHERENT to > invalidate CPU caches before the region is used. > > Successful invocation of attach_target() indicates that DPA has been > newly assigned to a given HPA in the dynamic region creation flow. > However, attach_target() is also reused in the autodiscovery flow where > the region was activated by platform firmware. In that case there is no > need to invalidate caches because that region is already in active use > and nothing about the autodiscovery flow modifies the HPA-to-DPA > relationship. > > Fixes: a32320b71f08 ("cxl/region: Add region autodiscovery") > Signed-off-by: Dan Williams Reviewed-by: Dave Jiang > --- > drivers/cxl/core/region.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c > index 52bbf6268d5f..b2fd67fcebfb 100644 > --- a/drivers/cxl/core/region.c > +++ b/drivers/cxl/core/region.c > @@ -1674,6 +1674,7 @@ static int cxl_region_attach(struct cxl_region *cxlr, > if (rc) > goto err_decrement; > p->state = CXL_CONFIG_ACTIVE; > + set_bit(CXL_REGION_F_INCOHERENT, &cxlr->flags); > } > > cxled->cxld.interleave_ways = p->interleave_ways; > @@ -1775,8 +1776,6 @@ static int attach_target(struct cxl_region *cxlr, > > down_read(&cxl_dpa_rwsem); > rc = cxl_region_attach(cxlr, cxled, pos); > - if (rc == 0) > - set_bit(CXL_REGION_F_INCOHERENT, &cxlr->flags); > up_read(&cxl_dpa_rwsem); > up_write(&cxl_region_rwsem); > return rc; >