Re: [PATCH v3 05/20] cxl: add function for type2 cxl regs setup

Jonathan Cameron
2024-09-13T17:32:44Z

On Sat, 7 Sep 2024 09:18:21 +0100
<alejandro.lucero-palau@amd.com> wrote:

> From: Alejandro Lucero <alucerop@amd.com>
>
> Create a new function for a type2 device initialising
> cxl_dev_state struct regarding cxl regs setup and mapping.
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> ---
> drivers/cxl/core/pci.c | 30 ++++++++++++++++++++++++++++++
> drivers/net/ethernet/sfc/efx_cxl.c | 6 ++++++
> include/linux/cxl/cxl.h | 2 ++
> 3 files changed, 38 insertions(+)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index bf57f081ef8f..9afcdd643866 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -1142,6 +1142,36 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> }
> EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL);
>
> +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds)
> +{
> + struct cxl_register_map map;
> + int rc;
> +
> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map,
> + &cxlds->capabilities);
> + if (!rc) {

I'd be tempted to wrap these two up in a separate function called
from here as the out of line good path is less than ideal from
readability point of view.

> + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs);
> + if (rc)
> + return rc;
> + }
> +
> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
> + &cxlds->reg_map, &cxlds->capabilities);
> + if (rc)
> + dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
> +
> + if (cxlds->capabilities & BIT(CXL_CM_CAP_CAP_ID_RAS)) {

If there are no component registers this isn't going to work yet this
tries anyway?

> + rc = cxl_map_component_regs(&cxlds->reg_map,
> + &cxlds->regs.component,
> + BIT(CXL_CM_CAP_CAP_ID_RAS));
> + if (rc)
> + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
> + }
> +
> + return rc;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, CXL);
> +