[PATCH v3 00/20] cxl: add Type2 device support

alejandro.lucero-palau
2024-09-07T08:19:21Z

From: Alejandro Lucero <alejandro.lucero-palau@amd.com>

v3 changes:

- cxl_dev_state not defined as opaque but only manipulated by accel drivers
through accessors.

- accessors names not identified as only for accel drivers.

- move pci code from pci driver (drivers/cxl/pci.c) to generic pci code
(drivers/cxl/core/pci.c).

- capabilities field from u8 to u32 and initialised by CXL regs discovering
code.

- add capabilities check and removing current check by CXL regs discovering
code.

- Not fail if CXL Device Registers not found. Not mandatory for Type2.

- add timeout in acquire_endpoint for solving a race with the endpoint port
creation.

- handle EPROBE_DEFER by sfc driver.

- Limiting interleave ways to 1 for accel driver HPA/DPA requests.

- factoring out interleave ways and granularity helpers from type2 region
creation patch.

- restricting region_creation for type2 to one endpoint decoder.

- add accessor for release_resource.

- handle errors and errors messages properly.

v2 changes:

I have removed the introduction about the concerns with BIOS/UEFI after the
discussion leading to confirm the need of the functionality implemented, at
least is some scenarios.

There are two main changes from the RFC:

1) Following concerns about drivers using CXL core without restrictions, the CXL
struct to work with is opaque to those drivers, therefore functions are
implemented for modifying or reading those structs indirectly.

2) The driver for using the added functionality is not a test driver but a real
one: the SFC ethernet network driver. It uses the CXL region mapped for PIO
buffers instead of regions inside PCIe BARs.

RFC:

Current CXL kernel code is focused on supporting Type3 CXL devices, aka memory
expanders. Type2 CXL devices, aka device accelerators, share some functionalities
but require some special handling.

First of all, Type2 are by definition specific to drivers doing something and not just
a memory expander, so it is expected to work with the CXL specifics. This implies the CXL
setup needs to be done by such a driver instead of by a generic CXL PCI driver
as for memory expanders. Most of such setup needs to use current CXL core code
and therefore needs to be accessible to those vendor drivers. This is accomplished
exporting opaque CXL structs and adding and exporting functions for working with
those structs indirectly.

Some of the patches are based on a patchset sent by Dan Williams [1] which was just
partially integrated, most related to making things ready for Type2 but none
related to specific Type2 support. Those patches based on Dan´s work have Dan´s
signing as co-developer, and a link to the original patch.

A final note about CXL.cache is needed. This patchset does not cover it at all,
although the emulated Type2 device advertises it. From the kernel point of view
supporting CXL.cache will imply to be sure the CXL path supports what the Type2
device needs. A device accelerator will likely be connected to a Root Switch,
but other configurations can not be discarded. Therefore the kernel will need to
check not just HPA, DPA, interleave and granularity, but also the available
CXL.cache support and resources in each switch in the CXL path to the Type2
device. I expect to contribute to this support in the following months, and
it would be good to discuss about it when possible.

[1] https://lore.kernel.org/linux-cxl/98b1f61a-e6c2-71d4-c368-50d958501b0c@intel.com/T/

Alejandro Lucero (20):
cxl: add type2 device basic support
cxl: add capabilities field to cxl_dev_state and cxl_port
cxl/pci: add check for validating capabilities
cxl: move pci generic code
cxl: add function for type2 cxl regs setup
cxl: add functions for resource request/release by a driver
cxl: harden resource_contains checks to handle zero size resources
cxl: add function for setting media ready by a driver
cxl: support type2 memdev creation
cxl: indicate probe deferral
cxl: define a driver interface for HPA free space enumaration
efx: use acquire_endpoint when looking for free HPA
cxl: define a driver interface for DPA allocation
cxl: make region type based on endpoint type
cxl/region: factor out interleave ways setup
cxl/region: factor out interleave granularity setup
cxl: allow region creation by type2 drivers
cxl: preclude device memory to be used for dax
cxl: add function for obtaining params from a region
efx: support pio mapping based on cxl

drivers/cxl/core/cdat.c | 3 +
drivers/cxl/core/hdm.c | 158 ++++++++--
drivers/cxl/core/memdev.c | 174 +++++++++++
drivers/cxl/core/pci.c | 111 +++++++
drivers/cxl/core/port.c | 11 +-
drivers/cxl/core/region.c | 417 ++++++++++++++++++++++----
drivers/cxl/core/regs.c | 29 +-
drivers/cxl/cxl.h | 14 +-
drivers/cxl/cxlmem.h | 7 +
drivers/cxl/cxlpci.h | 19 +-
drivers/cxl/mem.c | 21 +-
drivers/cxl/pci.c | 90 ++----
drivers/net/ethernet/sfc/Makefile | 2 +-
drivers/net/ethernet/sfc/ef10.c | 32 +-
drivers/net/ethernet/sfc/efx.c | 19 ++
drivers/net/ethernet/sfc/efx_cxl.c | 180 +++++++++++
drivers/net/ethernet/sfc/efx_cxl.h | 29 ++
drivers/net/ethernet/sfc/mcdi_pcol.h | 12 +
drivers/net/ethernet/sfc/net_driver.h | 8 +
drivers/net/ethernet/sfc/nic.h | 2 +
include/linux/cxl/cxl.h | 81 +++++
include/linux/cxl/pci.h | 23 ++
22 files changed, 1237 insertions(+), 205 deletions(-)
create mode 100644 drivers/net/ethernet/sfc/efx_cxl.c
create mode 100644 drivers/net/ethernet/sfc/efx_cxl.h
create mode 100644 include/linux/cxl/cxl.h
create mode 100644 include/linux/cxl/pci.h

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2.17.1