Re: [PATCH 2/3] cxl/region: Add sysfs attribute for locality attributes of CXL regions

[Dave Jiang <dave.jiang@intel.com>]

On 12/20/23 13:26, Dave Jiang wrote:
> 
> 
> On 12/19/23 09:44, Jonathan Cameron wrote:
>> On Tue, 12 Dec 2023 12:30:47 -0700
>> Dave Jiang <dave.jiang@intel.com> wrote:
>>
>>> On 12/11/23 02:06, Brice Goglin wrote:
>>>> Le 08/12/2023 à 00:31, Dave Jiang a écrit :  
>>>>> Add read/write latencies and bandwidth sysfs attributes for the enabled CXL
>>>>> region. The bandwidth is the aggregated bandwidth of all devices that
>>>>> contributes to the CXL region. The latency is the worst latency of the
>>>>> device amongst all the devices that contributes to the CXL region.  
>>>>
>>>>
>>>> Hello
>>>>
>>>> Which initiator do these bandwidths/latencies refer to? Local CPUs near the root port? This should be specified in the doc.  
>>>
>>> Currently I'm only storing the numbers from initiator pxm 0 to these targets in the hmat target list. I'm open to suggestions as to if a different way would be better.
>> Nearest node with CPUs would be better I think.
> 
> Is it possible to discover that? The SRAT MPDAS structure indicates the association of initiator and memory target domains. But it does not seem to make such associations for generic targets.

Answering my own question, looks like we need to go through hmat_update_target_attrs() and retrieve the best perf numbers via that function. Will make some mods to do that and post v15. This seems to be the way linux HMAT handling code is doing for normal initiator/target setup. 
> 
>>
>> Jonathan
>>
>