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From: Dave Jiang <dave.jiang@intel.com>
To: alejandro.lucero-palau@amd.com, linux-cxl@vger.kernel.org,
	dan.j.williams@intel.com
Cc: Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v1 2/3] cxl/region: Factor out interleave ways setup
Date: Tue, 24 Feb 2026 08:54:44 -0700	[thread overview]
Message-ID: <0e6a60ab-8b7b-4432-b22e-336c68b328e5@intel.com> (raw)
In-Reply-To: <20260224152645.3441489-3-alejandro.lucero-palau@amd.com>



On 2/24/26 8:26 AM, alejandro.lucero-palau@amd.com wrote:
> From: Alejandro Lucero <alucerop@amd.com>
> 
> Region creation based on Type3 devices is triggered from user space

s/is/can be/

Since there's also auto region creation.

> allowing memory combination through interleaving.
> 
> In preparation for kernel driven region creation, that is Type2 drivers
> triggering region creation backed with its advertised CXL memory, factor
> out a common helper from the user-sysfs region setup for interleave ways.
> 
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>

> ---
>  drivers/cxl/core/region.c | 41 +++++++++++++++++++++++++--------------
>  1 file changed, 26 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index cac33c99fe6a..3ef4ccf1c92b 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -485,22 +485,14 @@ static ssize_t interleave_ways_show(struct device *dev,
>  
>  static const struct attribute_group *get_cxl_region_target_group(void);
>  
> -static ssize_t interleave_ways_store(struct device *dev,
> -				     struct device_attribute *attr,
> -				     const char *buf, size_t len)
> +static int set_interleave_ways(struct cxl_region *cxlr, int val)
>  {
> -	struct cxl_region *cxlr = to_cxl_region(dev);
>  	struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
>  	struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
>  	struct cxl_region_params *p = &cxlr->params;
> -	unsigned int val, save;
> -	int rc;
> +	int save, rc;
>  	u8 iw;
>  
> -	rc = kstrtouint(buf, 0, &val);
> -	if (rc)
> -		return rc;
> -
>  	rc = ways_to_eiw(val, &iw);
>  	if (rc)
>  		return rc;
> @@ -515,9 +507,7 @@ static ssize_t interleave_ways_store(struct device *dev,
>  		return -EINVAL;
>  	}
>  
> -	ACQUIRE(rwsem_write_kill, rwsem)(&cxl_rwsem.region);
> -	if ((rc = ACQUIRE_ERR(rwsem_write_kill, &rwsem)))
> -		return rc;
> +	lockdep_assert_held_write(&cxl_rwsem.region);
>  
>  	if (p->state >= CXL_CONFIG_INTERLEAVE_ACTIVE)
>  		return -EBUSY;
> @@ -525,10 +515,31 @@ static ssize_t interleave_ways_store(struct device *dev,
>  	save = p->interleave_ways;
>  	p->interleave_ways = val;
>  	rc = sysfs_update_group(&cxlr->dev.kobj, get_cxl_region_target_group());
> -	if (rc) {
> +	if (rc)
>  		p->interleave_ways = save;
> +
> +	return rc;
> +}
> +
> +static ssize_t interleave_ways_store(struct device *dev,
> +				     struct device_attribute *attr,
> +				     const char *buf, size_t len)
> +{
> +	struct cxl_region *cxlr = to_cxl_region(dev);
> +	unsigned int val;
> +	int rc;
> +
> +	rc = kstrtouint(buf, 0, &val);
> +	if (rc)
> +		return rc;
> +
> +	ACQUIRE(rwsem_write_kill, rwsem)(&cxl_rwsem.region);
> +	if ((rc = ACQUIRE_ERR(rwsem_write_kill, &rwsem)))
> +		return rc;
> +
> +	rc = set_interleave_ways(cxlr, val);
> +	if (rc)
>  		return rc;
> -	}
>  
>  	return len;
>  }


  reply	other threads:[~2026-02-24 15:54 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-24 15:26 [PATCH v1 0/3] cxl region changes for Type2 support alejandro.lucero-palau
2026-02-24 15:26 ` [PATCH v1 1/3] cxl: Make region type based on endpoint type alejandro.lucero-palau
2026-02-24 16:04   ` Gregory Price
2026-02-24 15:26 ` [PATCH v1 2/3] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2026-02-24 15:54   ` Dave Jiang [this message]
2026-02-24 16:21     ` Alejandro Lucero Palau
2026-02-24 16:05   ` Gregory Price
2026-02-24 15:26 ` [PATCH v1 3/3] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2026-02-24 16:06   ` Gregory Price
2026-02-24 16:13   ` Dave Jiang
2026-02-24 15:39 ` [PATCH v1 0/3] cxl region changes for Type2 support Dave Jiang
2026-02-24 16:20   ` Alejandro Lucero Palau
2026-02-24 16:06 ` Gregory Price

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