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X-CSE-ConnectionGUID: NUV28q2TT1u/zSqAr08cYA== X-CSE-MsgGUID: 0F7U07uIRg+VE37CJDxiyA== X-IronPort-AV: E=McAfee;i="6700,10204,11260"; a="43351499" X-IronPort-AV: E=Sophos;i="6.12,165,1728975600"; d="scan'208";a="43351499" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2024 15:32:41 -0800 X-CSE-ConnectionGUID: pSm2zkgnTme4QUg/1tD37w== X-CSE-MsgGUID: 8cd1c+RwTe6T/Ze6FGs1wQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,165,1728975600"; d="scan'208";a="90174107" Received: from kcaccard-desk.amr.corp.intel.com (HELO [10.125.108.254]) ([10.125.108.254]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Nov 2024 15:32:41 -0800 Message-ID: <104f5fd2-2519-4497-9ebc-2ad17b415c2b@intel.com> Date: Mon, 18 Nov 2024 16:32:39 -0700 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 06/27] cxl: add function for type2 cxl regs setup To: alejandro.lucero-palau@amd.com, linux-cxl@vger.kernel.org, netdev@vger.kernel.org, dan.j.williams@intel.com, martin.habets@xilinx.com, edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, edumazet@google.com Cc: Alejandro Lucero References: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> <20241118164434.7551-7-alejandro.lucero-palau@amd.com> Content-Language: en-US From: Dave Jiang In-Reply-To: <20241118164434.7551-7-alejandro.lucero-palau@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/18/24 9:44 AM, alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero > > Create a new function for a type2 device initialising > cxl_dev_state struct regarding cxl regs setup and mapping. > > Signed-off-by: Alejandro Lucero Reviewed-by: Dave Jiang > --- > drivers/cxl/core/pci.c | 47 ++++++++++++++++++++++++++++++++++++++++++ > include/cxl/cxl.h | 2 ++ > 2 files changed, 49 insertions(+) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index bfc5e96e3cb9..8b9aa2c578e1 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -1096,6 +1096,53 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > } > EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); > > +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, > + struct cxl_dev_state *cxlds) > +{ > + struct cxl_register_map map; > + int rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > + cxlds->capabilities); > + /* > + * This call returning a non-zero value is not considered an error since > + * these regs are not mandatory for Type2. If they do exist then mapping > + * them should not fail. > + */ > + if (rc) > + return 0; > + > + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); > +} > + > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) > +{ > + int rc; > + > + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); > + if (rc) > + return rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > + &cxlds->reg_map, cxlds->capabilities); > + if (rc) { > + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); > + return rc; > + } > + > + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) > + return rc; > + > + rc = cxl_map_component_regs(&cxlds->reg_map, > + &cxlds->regs.component, > + BIT(CXL_CM_CAP_CAP_ID_RAS)); > + if (rc) > + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); > + > + return rc; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, CXL); > + > int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) > { > int speed, bw; > diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h > index ab243ab8024f..a88d3475e551 100644 > --- a/include/cxl/cxl.h > +++ b/include/cxl/cxl.h > @@ -5,6 +5,7 @@ > #define __CXL_H > > #include > +#include > > enum cxl_resource { > CXL_RES_DPA, > @@ -52,4 +53,5 @@ bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, > unsigned long *expected_caps, > unsigned long *current_caps, > bool is_subset); > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); > #endif