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From: Shrihari E S <shrihari.s@samsung.com>
To: jic23@kernel.org, junjie.cao@intel.com,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	qemu-devel@nongnu.org
Cc: shrihari.s@samsung.com, arun.george@samsung.com,
	cpgs@samsung.com, dave@stgolabs.net, dongjoo.seo1@samsung.com,
	gost.dev@samsung.com, s.neeraj@samsung.com,
	vikash.k5@samsung.com
Subject: [RFC V2 09/10] hw/cxl: Wire SVC and Dev3 capability to CXL Type 3 device
Date: Wed, 26 Aug 2026 11:04:09 +0530	[thread overview]
Message-ID: <1437941060.21787732282637.JavaMail.epsvc@epcpadp2new> (raw)
In-Reply-To: <20260826053410.1322176-1-shrihari.s@samsung.com>

Adds SVC and Dev3 capability to CXL type 3 device to make
it work as a UIO completer.

Signed-off-by: Shrihari E S <shrihari.s@samsung.com>
Signed-off-by: Dongjoo Seo <dongjoo.seo1@samsung.com>
---
 hw/mem/cxl_type3.c          | 15 +++++++++++++++
 include/hw/cxl/cxl_device.h |  1 +
 2 files changed, 16 insertions(+)

diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 0adf2e8b3e..74ddcf6e58 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1195,6 +1195,20 @@ void ct3_realize(PCIDevice *pci_dev, Error **errp)
     pcie_doe_init(pci_dev, &ct3d->doe_comp, 0x1b0, doe_comp_prot, true,
                   CXL_T3_MSIX_PCIE_DOE_COMPLIANCE);
 
+    if (ct3d->svc) {
+        /* SVC capability of the type3 device */
+        rc = pcie_svc_cap_init(pci_dev, 0x200 + PCI_ERR_SIZEOF, errp);
+        if ((rc >= 0) && ct3d->flitmode && ct3d->uio_comp_capable) {
+
+            /*
+             * The Dev3 Capability is initialized  after AER in the PCIe config
+             * space. Also initializing CXL type3 device as a UIO completer.
+             */
+            pcie_dev3_cap_init(pci_dev, 0x200 + PCI_ERR_SIZEOF + PCI_SVC_SIZEOF,
+                               false, true, errp);
+        }
+    }
+
     /* Set default value for patrol scrub attributes */
     ct3d->patrol_scrub_attrs.scrub_cycle_cap =
                            CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_DEFAULT |
@@ -1560,6 +1574,7 @@ static const Property ct3_props[] = {
                                 width, PCIE_LINK_WIDTH_16),
     DEFINE_PROP_BOOL("x-256b-flit", CXLType3Dev, flitmode, false),
     DEFINE_PROP_BOOL("hdm-db", CXLType3Dev, hdmdb, false),
+    DEFINE_PROP_BOOL("x-svc", CXLType3Dev, svc, false),
     DEFINE_PROP_BOOL("x-uio", CXLType3Dev, uio_comp_capable, false),
     DEFINE_PROP_UINT16("chmu-port", CXLType3Dev, cxl_dstate.chmu[0].port, 0),
 };
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 3d92d3f46c..5505aefe37 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -885,6 +885,7 @@ struct CXLType3Dev {
     bool flitmode;
     bool uio_comp_capable;
     bool uio_enabled;
+    bool svc;
 
     /* DOE */
     DOECap doe_cdat;
-- 
2.34.1



  parent reply	other threads:[~2026-08-26  8:18 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20260826052014epcas5p11846c6a40fcec4ec4ba441ceb26e5dcc@epcas5p1.samsung.com>
     [not found] ` <20260826053410.1322176-1-shrihari.s@samsung.com>
2026-08-26  5:34   ` [RFC V2 01/10] hw/pci: Refactor flitmode from PCIESlot to PCIEPort Shrihari E S
2026-08-26  5:34   ` [RFC V2 02/10] hw/pci: Move 'x-256b-flit' property from cxl_root_port to pcie_root_port Shrihari E S
2026-08-26  5:34   ` [RFC V2 03/10] hw/pci: Add SVC capability and UIO properties to PCIe ports Shrihari E S
2026-08-26  5:34   ` [RFC V2 04/10] hw/cxl: Add Streamlined Virtual Channel (SVC) property to CXL ports Shrihari E S
2026-08-26  5:34   ` [RFC V2 05/10] hw/cxl: Wire UIO capability into HDM decoder and DVSEC registers Shrihari E S
2026-08-26  5:34   ` [RFC V2 06/10] hw/pci: Add PCIe Streamlined Virtual Channel (SVC) capability Shrihari E S
2026-08-26  5:34   ` [RFC V2 07/10] hw/pci: hw/cxl: Wire SVC initialization into port realize functions Shrihari E S
2026-08-26  5:34   ` [RFC V2 08/10] hw/pci: Add PCIe Device3 capability support Shrihari E S
2026-08-26  5:34   ` Shrihari E S [this message]
2026-08-26  5:34   ` [RFC V2 10/10] cxl: Add documentation for CXL UIO support Shrihari E S

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