From: Dave Jiang <dave.jiang@intel.com>
To: ira.weiny@intel.com, Dan Williams <dan.j.williams@intel.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>,
Bjorn Helgaas <helgaas@kernel.org>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Steven Rostedt <rostedt@goodmis.org>,
linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org
Subject: Re: [PATCH 01/11] cxl/pci: Add generic MSI-X/MSI irq support
Date: Tue, 15 Nov 2022 14:41:15 -0700 [thread overview]
Message-ID: <176515c1-ecdb-7772-f2c4-521921295b20@intel.com> (raw)
In-Reply-To: <20221110185758.879472-2-ira.weiny@intel.com>
On 11/10/2022 10:57 AM, ira.weiny@intel.com wrote:
> From: Davidlohr Bueso <dave@stgolabs.net>
>
> Currently the only CXL features targeted for irq support require their
> message numbers to be within the first 16 entries. The device may
> however support less than 16 entries depending on the support it
> provides.
>
> Attempt to allocate these 16 irq vectors. If the device supports less
> then the PCI infrastructure will allocate that number. Store the number
> of vectors actually allocated in the device state for later use
> by individual functions.
>
> Upon successful allocation, users can plug in their respective isr at
> any point thereafter, for example, if the irq setup is not done in the
> PCI driver, such as the case of the CXL-PMU.
>
> Cc: Bjorn Helgaas <helgaas@kernel.org>
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Co-developed-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>
> ---
> Changes from Ira
> Remove reviews
> Allocate up to a static 16 vectors.
> Change cover letter
> ---
> drivers/cxl/cxlmem.h | 3 +++
> drivers/cxl/cxlpci.h | 6 ++++++
> drivers/cxl/pci.c | 32 ++++++++++++++++++++++++++++++++
> 3 files changed, 41 insertions(+)
>
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 88e3a8e54b6a..b7b955ded3ac 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -211,6 +211,7 @@ struct cxl_endpoint_dvsec_info {
> * @info: Cached DVSEC information about the device.
> * @serial: PCIe Device Serial Number
> * @doe_mbs: PCI DOE mailbox array
> + * @nr_irq_vecs: Number of MSI-X/MSI vectors available
> * @mbox_send: @dev specific transport for transmitting mailbox commands
> *
> * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
> @@ -247,6 +248,8 @@ struct cxl_dev_state {
>
> struct xarray doe_mbs;
>
> + int nr_irq_vecs;
> +
> int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
> };
>
> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index eec597dbe763..b7f4e2f417d3 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -53,6 +53,12 @@
> #define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8)
> #define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16)
>
> +/*
> + * NOTE: Currently all the functions which are enabled for CXL require their
> + * vectors to be in the first 16. Use this as the max.
> + */
> +#define CXL_PCI_REQUIRED_VECTORS 16
> +
> /* Register Block Identifier (RBI) */
> enum cxl_regloc_type {
> CXL_REGLOC_RBI_EMPTY = 0,
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index faeb5d9d7a7a..62e560063e50 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -428,6 +428,36 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds)
> }
> }
>
> +static void cxl_pci_free_irq_vectors(void *data)
> +{
> + pci_free_irq_vectors(data);
> +}
> +
> +static void cxl_pci_alloc_irq_vectors(struct cxl_dev_state *cxlds)
> +{
> + struct device *dev = cxlds->dev;
> + struct pci_dev *pdev = to_pci_dev(dev);
> + int nvecs;
> + int rc;
> +
> + nvecs = pci_alloc_irq_vectors(pdev, 1, CXL_PCI_REQUIRED_VECTORS,
> + PCI_IRQ_MSIX | PCI_IRQ_MSI);
> + if (nvecs < 0) {
> + dev_dbg(dev, "Not enough interrupts; use polling instead.\n");
> + return;
> + }
> +
> + rc = devm_add_action_or_reset(dev, cxl_pci_free_irq_vectors, pdev);
> + if (rc) {
> + dev_dbg(dev, "Device managed call failed; interrupts disabled.\n");
> + /* some got allocated, clean them up */
> + cxl_pci_free_irq_vectors(pdev);
> + return;
> + }
> +
> + cxlds->nr_irq_vecs = nvecs;
> +}
> +
> static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> {
> struct cxl_register_map map;
> @@ -494,6 +524,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> if (rc)
> return rc;
>
> + cxl_pci_alloc_irq_vectors(cxlds);
> +
> cxlmd = devm_cxl_add_memdev(cxlds);
> if (IS_ERR(cxlmd))
> return PTR_ERR(cxlmd);
next prev parent reply other threads:[~2022-11-15 21:42 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-10 18:57 [PATCH 00/11] CXL: Process event logs ira.weiny
2022-11-10 18:57 ` [PATCH 01/11] cxl/pci: Add generic MSI-X/MSI irq support ira.weiny
2022-11-15 21:41 ` Dave Jiang [this message]
2022-11-16 14:53 ` Jonathan Cameron
2022-11-16 23:48 ` Ira Weiny
2022-11-17 11:20 ` Jonathan Cameron
2022-11-10 18:57 ` [PATCH 02/11] cxl/mem: Implement Get Event Records command ira.weiny
2022-11-15 21:54 ` Dave Jiang
2022-11-16 15:19 ` Jonathan Cameron
2022-11-17 0:47 ` Ira Weiny
2022-11-17 10:43 ` Jonathan Cameron
2022-11-18 23:26 ` Ira Weiny
2022-11-21 10:47 ` Jonathan Cameron
2022-11-28 23:30 ` Ira Weiny
2022-11-29 12:26 ` Jonathan Cameron
2022-11-30 5:09 ` Ira Weiny
2022-11-30 14:05 ` Jonathan Cameron
2022-11-10 18:57 ` [PATCH 03/11] cxl/mem: Implement Clear " ira.weiny
2022-11-15 22:09 ` Dave Jiang
2022-11-16 15:24 ` Jonathan Cameron
2022-11-16 15:45 ` Jonathan Cameron
2022-11-17 1:12 ` Ira Weiny
2022-11-17 1:07 ` Ira Weiny
2022-11-10 18:57 ` [PATCH 04/11] cxl/mem: Clear events on driver load ira.weiny
2022-11-15 22:10 ` Dave Jiang
2022-11-10 18:57 ` [PATCH 05/11] cxl/mem: Trace General Media Event Record ira.weiny
2022-11-15 22:25 ` Dave Jiang
2022-11-16 15:31 ` Jonathan Cameron
2022-11-17 1:18 ` Ira Weiny
2022-11-10 18:57 ` [PATCH 06/11] cxl/mem: Trace DRAM " ira.weiny
2022-11-15 22:26 ` Dave Jiang
2022-11-10 18:57 ` [PATCH 07/11] cxl/mem: Trace Memory Module " ira.weiny
2022-11-15 22:39 ` Dave Jiang
2022-11-16 15:35 ` Jonathan Cameron
2022-11-17 1:23 ` Ira Weiny
2022-11-17 11:22 ` Jonathan Cameron
2022-11-30 9:30 ` Ira Weiny
2022-11-22 22:36 ` Steven Rostedt
2022-11-10 18:57 ` [PATCH 08/11] cxl/mem: Wire up event interrupts ira.weiny
2022-11-15 23:13 ` Dave Jiang
2022-11-17 1:38 ` Ira Weiny
2022-11-16 14:40 ` Jonathan Cameron
2022-11-30 9:11 ` Ira Weiny
2022-11-10 18:57 ` [PATCH 09/11] cxl/test: Add generic mock events ira.weiny
2022-11-16 16:00 ` Jonathan Cameron
2022-11-29 18:29 ` Ira Weiny
2022-11-10 18:57 ` [PATCH 10/11] cxl/test: Add specific events ira.weiny
2022-11-16 16:08 ` Jonathan Cameron
2022-11-10 18:57 ` [PATCH 11/11] cxl/test: Simulate event log overflow ira.weiny
2022-11-16 16:10 ` Jonathan Cameron
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