From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>,
Ben Widawsky <ben.widawsky@intel.com>, <vishal.l.verma@intel.com>,
<nvdimm@lists.linux.dev>, <alison.schofield@intel.com>,
<ira.weiny@intel.com>
Subject: Re: [PATCH v4 18/21] cxl/bus: Populate the target list at decoder create
Date: Fri, 10 Sep 2021 10:57:04 +0100 [thread overview]
Message-ID: <20210910105704.000060c4@Huawei.com> (raw)
In-Reply-To: <163116439000.2460985.11713777051267946018.stgit@dwillia2-desk3.amr.corp.intel.com>
On Wed, 8 Sep 2021 22:13:10 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> As found by cxl_test, the implementation populated the target_list for
> the single dport exceptional case, it missed populating the target_list
> for the typical multi-dport case. Root decoders always know their target
> list at the beginning of time, and even switch-level decoders should
> have a target list of one or more zeros by default, depending on the
> interleave-ways setting.
>
> Walk the hosting port's dport list and populate based on the passed in
> map.
>
> Move devm_cxl_add_passthrough_decoder() out of line now that it does the
> work of generating a target_map.
>
> Before:
> $ cat /sys/bus/cxl/devices/root2/decoder*/target_list
> 0
>
> 0
>
> After:
> $ cat /sys/bus/cxl/devices/root2/decoder*/target_list
> 0
> 0,1,2,3
> 0
> 0,1,2,3
>
> Where root2 is a CXL topology root object generated by 'cxl_test'.
>
> Acked-by: Ben Widawsky <ben.widawsky@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/acpi.c | 13 +++++++-
> drivers/cxl/core/bus.c | 80 +++++++++++++++++++++++++++++++++++++++++-------
> drivers/cxl/cxl.h | 25 ++++++---------
> 3 files changed, 91 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index d31a97218593..9d881eacdae5 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -52,6 +52,12 @@ static int cxl_acpi_cfmws_verify(struct device *dev,
> return -EINVAL;
> }
>
> + if (CFMWS_INTERLEAVE_WAYS(cfmws) > CXL_DECODER_MAX_INTERLEAVE) {
> + dev_err(dev, "CFMWS Interleave Ways (%d) too large\n",
> + CFMWS_INTERLEAVE_WAYS(cfmws));
> + return -EINVAL;
> + }
> +
> expected_len = struct_size((cfmws), interleave_targets,
> CFMWS_INTERLEAVE_WAYS(cfmws));
>
> @@ -71,6 +77,7 @@ static int cxl_acpi_cfmws_verify(struct device *dev,
> static void cxl_add_cfmws_decoders(struct device *dev,
> struct cxl_port *root_port)
> {
> + int target_map[CXL_DECODER_MAX_INTERLEAVE];
> struct acpi_cedt_cfmws *cfmws;
> struct cxl_decoder *cxld;
> acpi_size len, cur = 0;
> @@ -83,6 +90,7 @@ static void cxl_add_cfmws_decoders(struct device *dev,
>
> while (cur < len) {
> struct acpi_cedt_header *c = cedt_subtable + cur;
> + int i;
>
> if (c->type != ACPI_CEDT_TYPE_CFMWS) {
> cur += c->length;
> @@ -108,6 +116,9 @@ static void cxl_add_cfmws_decoders(struct device *dev,
> continue;
> }
>
> + for (i = 0; i < CFMWS_INTERLEAVE_WAYS(cfmws); i++)
> + target_map[i] = cfmws->interleave_targets[i];
> +
> flags = cfmws_to_decoder_flags(cfmws->restrictions);
> cxld = devm_cxl_add_decoder(dev, root_port,
> CFMWS_INTERLEAVE_WAYS(cfmws),
> @@ -115,7 +126,7 @@ static void cxl_add_cfmws_decoders(struct device *dev,
> CFMWS_INTERLEAVE_WAYS(cfmws),
> CFMWS_INTERLEAVE_GRANULARITY(cfmws),
> CXL_DECODER_EXPANDER,
> - flags);
> + flags, target_map);
>
> if (IS_ERR(cxld)) {
> dev_err(dev, "Failed to add decoder for %#llx-%#llx\n",
> diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
> index 8073354ba232..176bede30c55 100644
> --- a/drivers/cxl/core/bus.c
> +++ b/drivers/cxl/core/bus.c
> @@ -453,11 +453,38 @@ int cxl_add_dport(struct cxl_port *port, struct device *dport_dev, int port_id,
> }
> EXPORT_SYMBOL_GPL(cxl_add_dport);
>
> +static int decoder_populate_targets(struct device *host,
> + struct cxl_decoder *cxld,
> + struct cxl_port *port, int *target_map,
> + int nr_targets)
> +{
> + int rc = 0, i;
> +
> + if (!target_map)
> + return 0;
> +
> + device_lock(&port->dev);
> + for (i = 0; i < nr_targets; i++) {
> + struct cxl_dport *dport = find_dport(port, target_map[i]);
> +
> + if (!dport) {
> + rc = -ENXIO;
> + break;
> + }
> + dev_dbg(host, "%s: target: %d\n", dev_name(dport->dport), i);
> + cxld->target[i] = dport;
> + }
> + device_unlock(&port->dev);
> +
> + return rc;
> +}
> +
> static struct cxl_decoder *
> -cxl_decoder_alloc(struct cxl_port *port, int nr_targets, resource_size_t base,
> - resource_size_t len, int interleave_ways,
> - int interleave_granularity, enum cxl_decoder_type type,
> - unsigned long flags)
> +cxl_decoder_alloc(struct device *host, struct cxl_port *port, int nr_targets,
> + resource_size_t base, resource_size_t len,
> + int interleave_ways, int interleave_granularity,
> + enum cxl_decoder_type type, unsigned long flags,
> + int *target_map)
> {
> struct cxl_decoder *cxld;
> struct device *dev;
> @@ -493,10 +520,10 @@ cxl_decoder_alloc(struct cxl_port *port, int nr_targets, resource_size_t base,
> .target_type = type,
> };
>
> - /* handle implied target_list */
> - if (interleave_ways == 1)
> - cxld->target[0] =
> - list_first_entry(&port->dports, struct cxl_dport, list);
> + rc = decoder_populate_targets(host, cxld, port, target_map, nr_targets);
> + if (rc)
> + goto err;
> +
> dev = &cxld->dev;
> device_initialize(dev);
> device_set_pm_not_required(dev);
> @@ -519,14 +546,19 @@ struct cxl_decoder *
> devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets,
> resource_size_t base, resource_size_t len,
> int interleave_ways, int interleave_granularity,
> - enum cxl_decoder_type type, unsigned long flags)
> + enum cxl_decoder_type type, unsigned long flags,
> + int *target_map)
> {
> struct cxl_decoder *cxld;
> struct device *dev;
> int rc;
>
> - cxld = cxl_decoder_alloc(port, nr_targets, base, len, interleave_ways,
> - interleave_granularity, type, flags);
> + if (nr_targets > CXL_DECODER_MAX_INTERLEAVE)
> + return ERR_PTR(-EINVAL);
> +
> + cxld = cxl_decoder_alloc(host, port, nr_targets, base, len,
> + interleave_ways, interleave_granularity, type,
> + flags, target_map);
> if (IS_ERR(cxld))
> return cxld;
>
> @@ -550,6 +582,32 @@ devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets,
> }
> EXPORT_SYMBOL_GPL(devm_cxl_add_decoder);
>
> +/*
> + * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
> + * single ported host-bridges need not publish a decoder capability when a
> + * passthrough decode can be assumed, i.e. all transactions that the uport sees
> + * are claimed and passed to the single dport. Default the range a 0-base
> + * 0-length until the first CXL region is activated.
> + */
> +struct cxl_decoder *devm_cxl_add_passthrough_decoder(struct device *host,
> + struct cxl_port *port)
> +{
> + struct cxl_dport *dport;
> + int target_map[1];
> +
> + device_lock(&port->dev);
> + dport = list_first_entry_or_null(&port->dports, typeof(*dport), list);
> + device_unlock(&port->dev);
> +
> + if (!dport)
> + return ERR_PTR(-ENXIO);
> +
> + target_map[0] = dport->port_id;
> + return devm_cxl_add_decoder(host, port, 1, 0, 0, 1, PAGE_SIZE,
> + CXL_DECODER_EXPANDER, 0, target_map);
> +}
> +EXPORT_SYMBOL_GPL(devm_cxl_add_passthrough_decoder);
> +
> /**
> * __cxl_driver_register - register a driver for the cxl bus
> * @cxl_drv: cxl driver structure to attach
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index c5152718267e..84b8836c1f91 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -180,6 +180,12 @@ enum cxl_decoder_type {
> CXL_DECODER_EXPANDER = 3,
> };
>
> +/*
> + * Current specification goes up to 8, double that seems a reasonable
> + * software max for the foreseeable future
> + */
> +#define CXL_DECODER_MAX_INTERLEAVE 16
> +
> /**
> * struct cxl_decoder - CXL address range decode configuration
> * @dev: this decoder's device
> @@ -284,22 +290,11 @@ struct cxl_decoder *
> devm_cxl_add_decoder(struct device *host, struct cxl_port *port, int nr_targets,
> resource_size_t base, resource_size_t len,
> int interleave_ways, int interleave_granularity,
> - enum cxl_decoder_type type, unsigned long flags);
> -
> -/*
> - * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
> - * single ported host-bridges need not publish a decoder capability when a
> - * passthrough decode can be assumed, i.e. all transactions that the uport sees
> - * are claimed and passed to the single dport. Default the range a 0-base
> - * 0-length until the first CXL region is activated.
> - */
> -static inline struct cxl_decoder *
> -devm_cxl_add_passthrough_decoder(struct device *host, struct cxl_port *port)
> -{
> - return devm_cxl_add_decoder(host, port, 1, 0, 0, 1, PAGE_SIZE,
> - CXL_DECODER_EXPANDER, 0);
> -}
> + enum cxl_decoder_type type, unsigned long flags,
> + int *target_map);
>
> +struct cxl_decoder *devm_cxl_add_passthrough_decoder(struct device *host,
> + struct cxl_port *port);
> extern struct bus_type cxl_bus_type;
>
> struct cxl_driver {
>
next prev parent reply other threads:[~2021-09-10 9:57 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-09 5:11 [PATCH v4 00/21] cxl_test: Enable CXL Topology and UAPI regression tests Dan Williams
2021-09-09 5:11 ` [PATCH v4 01/21] libnvdimm/labels: Add uuid helpers Dan Williams
2021-09-09 5:11 ` [PATCH v4 02/21] libnvdimm/label: Add a helper for nlabel validation Dan Williams
2021-09-09 5:11 ` [PATCH v4 03/21] libnvdimm/labels: Introduce the concept of multi-range namespace labels Dan Williams
2021-09-09 13:09 ` Jonathan Cameron
2021-09-09 15:16 ` Dan Williams
2021-09-09 5:11 ` [PATCH v4 04/21] libnvdimm/labels: Fix kernel-doc for label.h Dan Williams
2021-09-10 8:38 ` Jonathan Cameron
2021-09-09 5:11 ` [PATCH v4 05/21] libnvdimm/label: Define CXL region labels Dan Williams
2021-09-09 15:58 ` Ben Widawsky
2021-09-09 18:38 ` Dan Williams
2021-09-09 5:12 ` [PATCH v4 06/21] libnvdimm/labels: Introduce CXL labels Dan Williams
2021-09-09 5:12 ` [PATCH v4 07/21] cxl/pci: Make 'struct cxl_mem' device type generic Dan Williams
2021-09-09 16:12 ` Ben Widawsky
2021-09-10 8:43 ` Jonathan Cameron
2021-09-09 5:12 ` [PATCH v4 08/21] cxl/pci: Clean up cxl_mem_get_partition_info() Dan Williams
2021-09-09 16:20 ` Ben Widawsky
2021-09-09 18:06 ` Dan Williams
2021-09-09 21:05 ` Ben Widawsky
2021-09-09 21:10 ` Dan Williams
2021-09-10 8:56 ` Jonathan Cameron
2021-09-13 22:19 ` [PATCH v5 " Dan Williams
2021-09-13 22:21 ` Dan Williams
2021-09-13 22:24 ` [PATCH v6 " Dan Williams
2021-09-09 5:12 ` [PATCH v4 09/21] cxl/mbox: Introduce the mbox_send operation Dan Williams
2021-09-09 16:34 ` Ben Widawsky
2021-09-10 8:58 ` Jonathan Cameron
2021-09-09 5:12 ` [PATCH v4 10/21] cxl/pci: Drop idr.h Dan Williams
2021-09-09 16:34 ` Ben Widawsky
2021-09-10 8:46 ` Jonathan Cameron
2021-09-09 5:12 ` [PATCH v4 11/21] cxl/mbox: Move mailbox and other non-PCI specific infrastructure to the core Dan Williams
2021-09-09 16:41 ` Ben Widawsky
2021-09-09 18:50 ` Dan Williams
2021-09-09 20:35 ` Ben Widawsky
2021-09-09 21:05 ` Dan Williams
2021-09-10 9:13 ` Jonathan Cameron
2021-09-09 5:12 ` [PATCH v4 12/21] cxl/pci: Use module_pci_driver Dan Williams
2021-09-09 5:12 ` [PATCH v4 13/21] cxl/mbox: Convert 'enabled_cmds' to DECLARE_BITMAP Dan Williams
2021-09-09 5:12 ` [PATCH v4 14/21] cxl/mbox: Add exclusive kernel command support Dan Williams
2021-09-09 17:02 ` Ben Widawsky
2021-09-10 9:33 ` Jonathan Cameron
2021-09-13 23:46 ` Dan Williams
2021-09-14 9:01 ` Jonathan Cameron
2021-09-14 12:22 ` Konstantin Ryabitsev
2021-09-14 14:39 ` Dan Williams
2021-09-14 15:51 ` Konstantin Ryabitsev
2021-09-14 19:03 ` [PATCH v5 " Dan Williams
2021-09-09 5:12 ` [PATCH v4 15/21] cxl/pmem: Translate NVDIMM label commands to CXL label commands Dan Williams
2021-09-09 17:22 ` Ben Widawsky
2021-09-09 19:03 ` Dan Williams
2021-09-09 20:32 ` Ben Widawsky
2021-09-10 9:39 ` Jonathan Cameron
2021-09-09 22:08 ` [PATCH v5 " Dan Williams
2021-09-10 9:40 ` Jonathan Cameron
2021-09-14 19:06 ` Dan Williams
2021-09-09 5:12 ` [PATCH v4 16/21] cxl/pmem: Add support for multiple nvdimm-bridge objects Dan Williams
2021-09-09 22:03 ` Dan Williams
2021-09-14 19:08 ` [PATCH v5 " Dan Williams
2021-09-09 5:13 ` [PATCH v4 17/21] tools/testing/cxl: Introduce a mocked-up CXL port hierarchy Dan Williams
2021-09-10 9:53 ` Jonathan Cameron
2021-09-10 18:46 ` Dan Williams
2021-09-14 19:14 ` [PATCH v5 " Dan Williams
2021-09-09 5:13 ` [PATCH v4 18/21] cxl/bus: Populate the target list at decoder create Dan Williams
2021-09-10 9:57 ` Jonathan Cameron [this message]
2021-09-09 5:13 ` [PATCH v4 19/21] cxl/mbox: Move command definitions to common location Dan Williams
2021-09-09 5:13 ` [PATCH v4 20/21] tools/testing/cxl: Introduce a mock memory device + driver Dan Williams
2021-09-10 10:09 ` Jonathan Cameron
2021-09-09 5:13 ` [PATCH v4 21/21] cxl/core: Split decoder setup into alloc + add Dan Williams
2021-09-10 10:33 ` Jonathan Cameron
2021-09-10 18:36 ` Dan Williams
2021-09-11 17:15 ` Ben Widawsky
2021-09-11 20:20 ` Dan Williams
2021-09-14 19:31 ` [PATCH v5 " Dan Williams
2021-09-21 14:24 ` Ben Widawsky
2021-09-21 16:18 ` Dan Williams
2021-09-21 19:22 ` [PATCH v6 " Dan Williams
2021-12-10 19:38 ` Nathan Chancellor
2021-12-10 19:41 ` Dan Williams
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