From: Ira Weiny <ira.weiny@intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org, Ben Widawsky <ben.widawsky@intel.com>,
kernel test robot <lkp@intel.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 05/10] cxl/pci: Make more use of cxl_register_map
Date: Sat, 9 Oct 2021 21:03:49 -0700 [thread overview]
Message-ID: <20211010040349.GI3114988@iweiny-DESK2.sc.intel.com> (raw)
In-Reply-To: <163381262522.716926.15040239940531720280.stgit@dwillia2-desk3.amr.corp.intel.com>
On Sat, Oct 09, 2021 at 01:51:13PM -0700, Dan Williams wrote:
> From: Ben Widawsky <ben.widawsky@intel.com>
>
> The structure exists to pass around information about register mapping.
> Use it for passing @barno and @block_offset, and eliminate duplicate
> local variables.
>
> The helpers that use @map do not care about @cxlm, so just pass them a
> pdev instead.
>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> [djbw: separate @base conversion]
> [djbw: reorder before cxl_pci_setup_regs() refactor to improver readability]
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
> Changes since v3:
> - Fix a 0day report about printing a resource_size_t
>
> drivers/cxl/pci.c | 55 ++++++++++++++++++++++-------------------------------
> 1 file changed, 23 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 21dd10a77eb3..f1de236ccd13 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -306,12 +306,13 @@ static int cxl_pci_setup_mailbox(struct cxl_mem *cxlm)
> return 0;
> }
>
> -static void __iomem *cxl_pci_map_regblock(struct cxl_mem *cxlm,
> - u8 bar, u64 offset)
> +static void __iomem *cxl_pci_map_regblock(struct pci_dev *pdev,
> + struct cxl_register_map *map)
> {
> void __iomem *addr;
> - struct device *dev = cxlm->dev;
> - struct pci_dev *pdev = to_pci_dev(dev);
> + int bar = map->barno;
> + struct device *dev = &pdev->dev;
> + resource_size_t offset = map->block_offset;
>
> /* Basic sanity check that BAR is big enough */
> if (pci_resource_len(pdev, bar) < offset) {
> @@ -326,15 +327,15 @@ static void __iomem *cxl_pci_map_regblock(struct cxl_mem *cxlm,
> return addr;
> }
>
> - dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %#llx\n",
> - bar, offset);
> + dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %pa\n",
> + bar, &offset);
>
> return addr;
> }
>
> -static void cxl_pci_unmap_regblock(struct cxl_mem *cxlm, void __iomem *base)
> +static void cxl_pci_unmap_regblock(struct pci_dev *pdev, void __iomem *base)
> {
> - pci_iounmap(to_pci_dev(cxlm->dev), base);
> + pci_iounmap(pdev, base);
> }
>
> static int cxl_pci_dvsec(struct pci_dev *pdev, int dvsec)
> @@ -360,12 +361,12 @@ static int cxl_pci_dvsec(struct pci_dev *pdev, int dvsec)
> return 0;
> }
>
> -static int cxl_probe_regs(struct cxl_mem *cxlm, void __iomem *base,
> +static int cxl_probe_regs(struct pci_dev *pdev, void __iomem *base,
> struct cxl_register_map *map)
> {
> struct cxl_component_reg_map *comp_map;
> struct cxl_device_reg_map *dev_map;
> - struct device *dev = cxlm->dev;
> + struct device *dev = &pdev->dev;
>
> switch (map->reg_type) {
> case CXL_REGLOC_RBI_COMPONENT:
> @@ -420,12 +421,13 @@ static int cxl_map_regs(struct cxl_mem *cxlm, struct cxl_register_map *map)
> return 0;
> }
>
> -static void cxl_decode_register_block(u32 reg_lo, u32 reg_hi,
> - u8 *bar, u64 *offset, u8 *reg_type)
> +static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi,
> + struct cxl_register_map *map)
> {
> - *offset = ((u64)reg_hi << 32) | (reg_lo & CXL_REGLOC_ADDR_MASK);
> - *bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo);
> - *reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo);
> + map->block_offset =
> + ((u64)reg_hi << 32) | (reg_lo & CXL_REGLOC_ADDR_MASK);
> + map->barno = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo);
> + map->reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo);
> }
>
> /**
> @@ -462,34 +464,23 @@ static int cxl_pci_setup_regs(struct cxl_mem *cxlm)
>
> for (i = 0, n_maps = 0; i < regblocks; i++, regloc += 8) {
> u32 reg_lo, reg_hi;
> - u8 reg_type;
> - u64 offset;
> - u8 bar;
>
> pci_read_config_dword(pdev, regloc, ®_lo);
> pci_read_config_dword(pdev, regloc + 4, ®_hi);
>
> - cxl_decode_register_block(reg_lo, reg_hi, &bar, &offset,
> - ®_type);
> + map = &maps[n_maps];
> + cxl_decode_regblock(reg_lo, reg_hi, map);
>
> /* Ignore unknown register block types */
> - if (reg_type > CXL_REGLOC_RBI_MEMDEV)
> + if (map->reg_type > CXL_REGLOC_RBI_MEMDEV)
> continue;
>
> - base = cxl_pci_map_regblock(cxlm, bar, offset);
> + base = cxl_pci_map_regblock(pdev, map);
> if (!base)
> return -ENOMEM;
>
> - map = &maps[n_maps];
> - map->barno = bar;
> - map->block_offset = offset;
> - map->reg_type = reg_type;
> -
> - ret = cxl_probe_regs(cxlm, base + offset, map);
> -
> - /* Always unmap the regblock regardless of probe success */
> - cxl_pci_unmap_regblock(cxlm, base);
> -
> + ret = cxl_probe_regs(pdev, base + map->block_offset, map);
> + cxl_pci_unmap_regblock(pdev, base);
> if (ret)
> return ret;
>
>
next prev parent reply other threads:[~2021-10-10 4:03 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-09 16:43 [PATCH v3 00/10] cxl_pci refactor for reusability Dan Williams
2021-10-09 16:44 ` [PATCH v3 01/10] cxl/pci: Convert register block identifiers to an enum Dan Williams
2021-10-09 16:44 ` [PATCH v3 02/10] cxl/pci: Remove dev_dbg for unknown register blocks Dan Williams
2021-10-09 16:48 ` Joe Perches
2021-10-09 18:04 ` Ben Widawsky
2021-10-09 16:44 ` [PATCH v3 03/10] cxl/pci: Fix NULL vs ERR_PTR confusion Dan Williams
2021-10-10 3:44 ` Ira Weiny
2021-10-15 16:15 ` Jonathan Cameron
2021-10-15 20:16 ` Dan Williams
2021-10-15 21:29 ` [PATCH v6 " Dan Williams
2021-10-09 16:44 ` [PATCH v3 04/10] cxl/pci: Remove pci request/release regions Dan Williams
2021-10-09 16:44 ` [PATCH v3 05/10] cxl/pci: Make more use of cxl_register_map Dan Williams
2021-10-09 19:04 ` kernel test robot
2021-10-09 20:51 ` [PATCH v4 " Dan Williams
2021-10-10 4:03 ` Ira Weiny [this message]
2021-10-13 23:53 ` [PATCH v5 " Dan Williams
2021-10-09 16:44 ` [PATCH v3 06/10] cxl/pci: Add @base to cxl_register_map Dan Williams
2021-10-10 4:20 ` Ira Weiny
2021-10-13 22:53 ` Dan Williams
2021-10-15 16:29 ` Jonathan Cameron
2021-10-15 16:56 ` Dan Williams
2021-10-13 23:57 ` [PATCH v5 " Dan Williams
2021-10-15 21:57 ` [PATCH v6 " Dan Williams
2021-10-18 9:30 ` Jonathan Cameron
2021-10-15 16:27 ` [PATCH v3 " Jonathan Cameron
2021-10-15 16:55 ` Dan Williams
2021-10-18 9:30 ` Jonathan Cameron
2021-10-09 16:44 ` [PATCH v3 07/10] cxl/pci: Split cxl_pci_setup_regs() Dan Williams
2021-10-10 4:44 ` Ira Weiny
2021-10-13 22:45 ` Ben Widawsky
2021-10-13 22:49 ` Dan Williams
2021-10-14 0:12 ` Ben Widawsky
2021-10-14 0:48 ` Dan Williams
2021-10-15 16:44 ` Jonathan Cameron
2021-10-15 17:00 ` Dan Williams
2021-10-15 23:30 ` [PATCH v6 " Dan Williams
2021-11-10 17:14 ` Jonathan Cameron
2021-11-10 17:30 ` Ben Widawsky
2021-11-10 17:43 ` Jonathan Cameron
2021-10-09 16:44 ` [PATCH v3 08/10] PCI: Add pci_find_dvsec_capability to find designated VSEC Dan Williams
2021-10-09 16:44 ` [PATCH v3 09/10] cxl/pci: Use pci core's DVSEC functionality Dan Williams
2021-10-11 13:35 ` Jonathan Cameron
2021-10-09 16:44 ` [PATCH v3 10/10] ocxl: " Dan Williams
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