From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Ben Widawsky <ben.widawsky@intel.com>
Cc: <linux-cxl@vger.kernel.org>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
"Ira Weiny" <ira.weiny@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 7/9] cxl/acpi: Map component registers for Root Ports
Date: Tue, 30 Nov 2021 13:22:25 +0000 [thread overview]
Message-ID: <20211130132225.00005cea@Huawei.com> (raw)
In-Reply-To: <20211129214721.1668325-8-ben.widawsky@intel.com>
On Mon, 29 Nov 2021 13:47:19 -0800
Ben Widawsky <ben.widawsky@intel.com> wrote:
> This implements the TODO in cxl_acpi for mapping component registers.
> cxl_acpi becomes the second consumer of CXL register block enumeration
> (cxl_pci being the first). Moving the functionality to cxl_core allows
> both of these drivers to use the functionality. Equally importantly it
> allows cxl_core to use the functionality in the future.
>
> CXL 2.0 root ports are similar to CXL 2.0 Downstream Ports with the main
> distinction being they're a part of the CXL 2.0 host bridge. While
> mapping their component registers is not immediately useful for the CXL
> drivers, the movement of register block enumeration into core is a vital
> step towards HDM decoder programming.
>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
next prev parent reply other threads:[~2021-11-30 13:22 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-29 21:47 [PATCH 0/9] CXL port prep work Ben Widawsky
2021-11-29 21:47 ` [PATCH 1/9] cxl: Rename CXL_MEM to CXL_PCI Ben Widawsky
2021-11-29 21:47 ` [PATCH 2/9] cxl: Flesh out register names Ben Widawsky
2021-11-29 21:47 ` [PATCH 3/9] cxl/pci: Extract device status check Ben Widawsky
2021-12-02 17:09 ` Dan Williams
2021-12-02 17:24 ` Ben Widawsky
2021-12-02 17:32 ` Dan Williams
2021-12-04 1:18 ` Ben Widawsky
2021-12-04 1:37 ` Dan Williams
2021-11-29 21:47 ` [PATCH 4/9] cxl/pci: Implement Interface Ready Timeout Ben Widawsky
2021-11-30 13:19 ` Jonathan Cameron
2021-12-02 4:45 ` [PATCH v2 " Ben Widawsky
2021-12-02 9:54 ` Jonathan Cameron
2021-11-29 21:47 ` [PATCH 5/9] cxl/pci: Don't poll doorbell for mailbox access Ben Widawsky
2021-11-29 21:47 ` [PATCH 6/9] cxl/pci: Add new DVSEC definitions Ben Widawsky
2021-11-29 21:47 ` [PATCH 7/9] cxl/acpi: Map component registers for Root Ports Ben Widawsky
2021-11-30 13:22 ` Jonathan Cameron [this message]
2021-12-04 4:37 ` Dan Williams
2021-12-04 5:13 ` Ben Widawsky
2021-12-15 15:04 ` Jonathan Cameron
2021-11-29 21:47 ` [PATCH 8/9] cxl: Introduce module_cxl_driver Ben Widawsky
2021-11-30 13:23 ` Jonathan Cameron
2021-11-29 21:47 ` [PATCH 9/9] cxl/core: Convert decoder range to resource Ben Widawsky
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