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From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Ben Widawsky <bwidawsk@kernel.org>,
	Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>, Robert Richter <rrichter@amd.com>
Subject: [PATCH 13/15] cxl/acpi: Rework devm_cxl_enumerate_ports() to support RCD mode
Date: Wed, 31 Aug 2022 10:16:01 +0200	[thread overview]
Message-ID: <20220831081603.3415-14-rrichter@amd.com> (raw)
In-Reply-To: <20220831081603.3415-1-rrichter@amd.com>

RCD mode has a different enumeration scheme other than in CXL VH mode.
An RCD is directly connected to an RCH without downstream and upstream
ports showing up in between in the PCI hierarchy. Due to the direct
connection of RCD and RCH, the host bridge is always the RCD's parent
instead of the grandparent. Modify devm_cxl_enumerate_ports()
respectively.

Implement this by introducing a function to determine the device's
downstream port. The 'for' loop is adjusted for RCD mode and in this
case find_cxl_port() will always find the host's associated port and
the loop iteration stops.

Signed-off-by: Robert Richter <rrichter@amd.com>
---
 drivers/cxl/core/port.c | 36 ++++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 61e9915162d5..08b99423dbf8 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1084,6 +1084,22 @@ static struct device *grandparent(struct device *dev)
 	return NULL;
 }
 
+static struct device *cxl_mem_dport_dev(struct cxl_memdev *cxlmd)
+{
+	struct device *dev = cxlmd->dev.parent;
+	struct pci_dev *pdev = to_pci_dev(cxlmd->dev.parent);
+
+	/*
+	 * An RCiEP is directly connected to the root bridge without
+	 * any PCI bridges/ports in between. Reduce the parent level
+	 * for those.
+	 */
+	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
+		return dev;
+
+	return dev->parent;
+}
+
 static void delete_endpoint(void *data)
 {
 	struct cxl_memdev *cxlmd = data;
@@ -1339,7 +1355,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd,
 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
 {
 	struct device *dev = &cxlmd->dev;
-	struct device *iter;
+	struct device *dport_dev;
 	int rc;
 
 	rc = devm_add_action_or_reset(&cxlmd->dev, cxl_detach_ep, cxlmd);
@@ -1352,25 +1368,21 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
 	 * attempt fails.
 	 */
 retry:
-	for (iter = dev; iter; iter = grandparent(iter)) {
-		struct device *dport_dev = grandparent(iter);
+	for (dport_dev = cxl_mem_dport_dev(cxlmd); dport_dev;
+	     dport_dev = grandparent(dport_dev)) {
 		struct device *uport_dev;
 		struct cxl_dport *dport;
 		struct cxl_port *port;
 
-		if (!dport_dev)
-			return 0;
-
 		uport_dev = dport_dev->parent;
 		if (!uport_dev) {
-			dev_warn(dev, "at %s no parent for dport: %s\n",
-				 dev_name(iter), dev_name(dport_dev));
+			dev_warn(dev, "no parent for dport: %s\n",
+				 dev_name(dport_dev));
 			return -ENXIO;
 		}
 
-		dev_dbg(dev, "scan: iter: %s dport_dev: %s parent: %s\n",
-			dev_name(iter), dev_name(dport_dev),
-			dev_name(uport_dev));
+		dev_dbg(dev, "scan: dport_dev: %s parent: %s\n",
+			dev_name(dport_dev), dev_name(uport_dev));
 		port = find_cxl_port(dport_dev, &dport);
 		if (port) {
 			dev_dbg(&cxlmd->dev,
@@ -1418,7 +1430,7 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_enumerate_ports, CXL);
 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
 				   struct cxl_dport **dport)
 {
-	return find_cxl_port(grandparent(&cxlmd->dev), dport);
+	return find_cxl_port(cxl_mem_dport_dev(cxlmd), dport);
 }
 EXPORT_SYMBOL_NS_GPL(cxl_mem_find_port, CXL);
 
-- 
2.30.2


  parent reply	other threads:[~2022-08-31  8:18 UTC|newest]

Thread overview: 101+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-31  8:15 [PATCH 00/15] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-08-31  8:15 ` [PATCH 01/15] cxl/core: Remove duplicate declaration of devm_cxl_iomap_block() Robert Richter
2022-08-31  8:54   ` Jonathan Cameron
2022-09-01  5:21     ` Robert Richter
2022-09-07 16:11   ` [PATCH 1/15] " Davidlohr Bueso
2022-09-09 10:38     ` Robert Richter
2022-09-08  5:44   ` [PATCH 01/15] " Dan Williams
2022-09-08 14:51     ` Robert Richter
2022-09-08 19:47       ` Dan Williams
2022-08-31  8:15 ` [PATCH 02/15] cxl/core: Check physical address before mapping it in devm_cxl_iomap_block() Robert Richter
2022-08-31  8:56   ` Jonathan Cameron
2022-09-01  5:31     ` Robert Richter
2022-09-08  5:48   ` Dan Williams
2022-09-09 12:19     ` Robert Richter
2022-09-16 18:04       ` Dan Williams
2022-09-28 10:28         ` Robert Richter
2022-09-30 19:07           ` Dan Williams
2022-08-31  8:15 ` [PATCH 03/15] cxl: Unify debug messages when calling devm_cxl_add_port() Robert Richter
2022-08-31  9:59   ` Jonathan Cameron
2022-09-01  5:36     ` Robert Richter
2022-09-06  7:30     ` Robert Richter
2022-09-06  8:52       ` Jonathan Cameron
2022-09-07 16:21   ` [PATCH 3/15] " Davidlohr Bueso
2022-09-08  5:53   ` [PATCH 03/15] " Dan Williams
2022-09-28 10:32     ` Robert Richter
2022-08-31  8:15 ` [PATCH 04/15] cxl: Unify debug messages when calling devm_cxl_add_dport() Robert Richter
2022-09-07 16:29   ` [PATCH 4/15] " Davidlohr Bueso
2022-09-08  5:55   ` [PATCH 04/15] " Dan Williams
2022-08-31  8:15 ` [PATCH 05/15] cxl/acpi: Add probe function to detect restricted CXL hosts in RCD mode Robert Richter
2022-08-31 10:08   ` Jonathan Cameron
2022-09-01  6:01     ` Robert Richter
2022-09-01 10:10       ` Jonathan Cameron
2022-09-06  7:19         ` Robert Richter
2022-09-06  8:53           ` Jonathan Cameron
2022-09-07 18:22   ` Bjorn Helgaas
2022-09-08  6:00   ` Dan Williams
2022-09-08  6:11   ` Dan Williams
2022-08-31  8:15 ` [PATCH 06/15] PCI/ACPI: Link host bridge to its ACPI fw node Robert Richter
2022-08-31 10:11   ` Jonathan Cameron
2022-09-07 18:37   ` Bjorn Helgaas
2022-09-07 20:15     ` Rafael J. Wysocki
2022-09-08  6:05   ` Dan Williams
2022-09-08 13:06     ` Rafael J. Wysocki
2022-09-08 19:45       ` Dan Williams
2022-09-09 10:20         ` Robert Richter
2022-09-14 22:11           ` Bjorn Helgaas
2022-09-16 23:16             ` Dan Williams
2022-09-08 13:04   ` Rafael J. Wysocki
2022-08-31  8:15 ` [PATCH 07/15] cxl/acpi: Check RCH's PCIe Host Bridge ACPI ID Robert Richter
2022-08-31 10:20   ` Jonathan Cameron
2022-09-01  6:16     ` Robert Richter
2022-09-01 10:14       ` Jonathan Cameron
2022-09-08  6:11   ` Dan Williams
2022-08-31  8:15 ` [PATCH 08/15] cxl/acpi: Check RCH's CXL DVSEC capabilities Robert Richter
2022-08-31 10:52   ` Jonathan Cameron
2022-08-31 11:12     ` Jonathan Cameron
2022-09-01  6:38       ` Robert Richter
2022-09-01 10:37         ` Jonathan Cameron
2022-09-06 10:20           ` Robert Richter
2022-09-01  6:30     ` Robert Richter
2022-09-01 10:23       ` Jonathan Cameron
2022-09-08  6:18   ` Dan Williams
2022-08-31  8:15 ` [PATCH 09/15] cxl/acpi: Determine PCI host bridge's ACPI UID Robert Richter
2022-08-31 11:00   ` Jonathan Cameron
2022-09-01  6:53     ` Robert Richter
2022-09-01 10:41       ` Jonathan Cameron
2022-09-08  6:18   ` Dan Williams
2022-09-08 20:47   ` Jonathan Zhang (Infra)
2022-09-08 21:10     ` Dan Williams
2022-09-08 21:35       ` Jonathan Zhang (Infra)
2022-09-08 22:31         ` Dan Williams
2022-09-08 22:41           ` Jonathan Zhang (Infra)
2022-08-31  8:15 ` [PATCH 10/15] cxl/acpi: Extract the RCH's RCRB base address from CEDT Robert Richter
2022-08-31 11:09   ` Jonathan Cameron
2022-09-01  7:04     ` Robert Richter
2022-08-31  8:15 ` [PATCH 11/15] cxl/acpi: Extract the host's component register base address from RCRB Robert Richter
2022-08-31 11:56   ` Jonathan Cameron
2022-09-01  7:38     ` Robert Richter
2022-09-01 11:00       ` Jonathan Cameron
2022-09-06 11:32         ` Robert Richter
2022-09-08 20:59   ` Jonathan Zhang (Infra)
2022-08-31  8:16 ` [PATCH 12/15] cxl/acpi: Skip devm_cxl_port_enumerate_dports() when in RCD mode Robert Richter
2022-08-31 11:58   ` Jonathan Cameron
2022-09-01  7:40     ` Robert Richter
2022-08-31  8:16 ` Robert Richter [this message]
2022-08-31 12:11   ` [PATCH 13/15] cxl/acpi: Rework devm_cxl_enumerate_ports() to support " Jonathan Cameron
2022-09-01  7:50     ` Robert Richter
2022-08-31  8:16 ` [PATCH 14/15] cxl/acpi: Enumerate ports in RCD mode to enable RCHs and RCDs Robert Richter
2022-08-31 12:16   ` Jonathan Cameron
2022-09-01  7:54     ` Robert Richter
2022-08-31  8:16 ` [PATCH 15/15] cxl/acpi: Specify module load order dependency for the cxl_acpi module Robert Richter
2022-09-16 18:12   ` Dan Williams
2022-08-31 12:23 ` [PATCH 00/15] cxl: Add support for Restricted CXL hosts (RCD mode) Jonathan Cameron
2022-09-01  8:19   ` Robert Richter
2022-09-08  6:41     ` Dan Williams
2022-09-08  5:43 ` Dan Williams
2022-09-08 18:52   ` Jonathan Zhang (Infra)
2022-09-08 19:51     ` Dan Williams
2022-09-08 20:36       ` Jonathan Zhang (Infra)
2022-09-08 21:02         ` Dan Williams
2022-09-16 18:16 ` Dan Williams

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