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From: Gregory Price <gourry.memverge@gmail.com>
To: qemu-devel@nongnu.org
Cc: jonathan.cameron@huawei.com, linux-cxl@vger.kernel.org,
	alison.schofield@intel.com, dave@stgolabs.net,
	a.manzanares@samsung.com, bwidawsk@kernel.org,
	Gregory Price <gregory.price@memverge.com>
Subject: [PATCH 2/2] hw/cxl: Allow CXL type-3 devices to be persistent or volatile
Date: Thu,  6 Oct 2022 19:37:02 -0400	[thread overview]
Message-ID: <20221006233702.18532-2-gregory.price@memverge.com> (raw)
In-Reply-To: <20221006233702.18532-1-gregory.price@memverge.com>

This commit enables setting one memory region for a type-3 device, but
that region may now be either a persistent region or volatile region.

Future work may enable setting both regions simultaneously, as this is
a possible configuration on a real type-3 device.  The scaffolding was
put in for this, but is left for further work.

The existing [memdev] property has been deprecated and will default the
memory region to a persistent memory region (although a user may assign
the region to a ram or file backed region).

There is presently no interface with which to expose a MemoryRegion's
real backing type (HostMemoryBackendRam/File), otherwise we could have
used File to imply pmem (or inspected HostMemoryBackendFile->is_pmem) to
deterine whether the backing device supported pmem mode.  This should be
considered for future work, as it would make creating an array of
HostMemory devices to represent DIMMs on a Single-Logical-Device
MemoryExpander fairly straightforward.

Signed-off-by: Gregory Price <gregory.price@memverge.com>
---
 hw/cxl/cxl-mailbox-utils.c  | 22 ++++++++++--------
 hw/mem/cxl_type3.c          | 46 +++++++++++++++++++++++++++++++++----
 include/hw/cxl/cxl_device.h |  7 +++++-
 3 files changed, 59 insertions(+), 16 deletions(-)

diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index bc1bb18844..dfec11a1b5 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -138,7 +138,7 @@ static ret_code cmd_firmware_update_get_info(struct cxl_cmd *cmd,
     } QEMU_PACKED *fw_info;
     QEMU_BUILD_BUG_ON(sizeof(*fw_info) != 0x50);
 
-    if (cxl_dstate->pmem_size < (256 << 20)) {
+    if (cxl_dstate->mem_size < (256 << 20)) {
         return CXL_MBOX_INTERNAL_ERROR;
     }
 
@@ -281,9 +281,10 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
 
     CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
     CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
-    uint64_t size = cxl_dstate->pmem_size;
 
-    if (!QEMU_IS_ALIGNED(size, 256 << 20)) {
+    if ((!QEMU_IS_ALIGNED(cxl_dstate->mem_size, 256 << 20)) ||
+        (!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, 256 << 20)) ||
+        (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, 256 << 20))) {
         return CXL_MBOX_INTERNAL_ERROR;
     }
 
@@ -293,8 +294,9 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
     /* PMEM only */
     snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0);
 
-    id->total_capacity = size / (256 << 20);
-    id->persistent_capacity = size / (256 << 20);
+    id->total_capacity = cxl_dstate->mem_size / (256 << 20);
+    id->persistent_capacity = cxl_dstate->pmem_size / (256 << 20);
+    id->volatile_capacity = cxl_dstate->vmem_size / (256 << 20);
     id->lsa_size = cvc->get_lsa_size(ct3d);
 
     *len = sizeof(*id);
@@ -312,16 +314,16 @@ static ret_code cmd_ccls_get_partition_info(struct cxl_cmd *cmd,
         uint64_t next_pmem;
     } QEMU_PACKED *part_info = (void *)cmd->payload;
     QEMU_BUILD_BUG_ON(sizeof(*part_info) != 0x20);
-    uint64_t size = cxl_dstate->pmem_size;
 
-    if (!QEMU_IS_ALIGNED(size, 256 << 20)) {
+    if ((!QEMU_IS_ALIGNED(cxl_dstate->mem_size, 256 << 20)) ||
+        (!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, 256 << 20)) ||
+        (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, 256 << 20))) {
         return CXL_MBOX_INTERNAL_ERROR;
     }
 
-    /* PMEM only */
-    part_info->active_vmem = 0;
+    part_info->active_vmem = cxl_dstate->vmem_size / (256 << 20);
     part_info->next_vmem = 0;
-    part_info->active_pmem = size / (256 << 20);
+    part_info->active_pmem = cxl_dstate->pmem_size / (256 << 20);
     part_info->next_pmem = 0;
 
     *len = sizeof(*part_info);
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 1837c1c83a..998461dac1 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -100,18 +100,47 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
     DeviceState *ds = DEVICE(ct3d);
     MemoryRegion *mr;
     char *name;
+    bool is_pmem = false;
 
-    if (!ct3d->hostmem) {
-        error_setg(errp, "memdev property must be set");
+    /*
+     * FIXME: For now we only allow a single host memory region.
+     * Handle the deprecated memdev property usage cases
+     */
+    if (!ct3d->hostmem && !ct3d->host_vmem && !ct3d->host_pmem) {
+        error_setg(errp, "at least one memdev property must be set");
         return false;
+    } else if (ct3d->hostmem && (ct3d->host_vmem || ct3d->host_pmem)) {
+        error_setg(errp, "deprecated [memdev] cannot be used with new "
+                         "persistent and volatile memdev properties");
+        return false;
+    } else if (ct3d->hostmem) {
+        warn_report("memdev is deprecated and defaults to pmem. "
+                    "Use (persistent|volatile)-memdev instead.");
+        is_pmem = true;
+    } else {
+        if (ct3d->host_vmem && ct3d->host_pmem) {
+            error_setg(errp, "Multiple memory devices not supported yet");
+            return false;
+        }
+        is_pmem = !!ct3d->host_pmem;
+        ct3d->hostmem = ct3d->host_pmem ? ct3d->host_pmem : ct3d->host_vmem;
     }
 
+    /*
+     * for now, since there is only one memdev, we can set the type
+     * based on whether this was a ram region or file region
+     */
     mr = host_memory_backend_get_memory(ct3d->hostmem);
     if (!mr) {
         error_setg(errp, "memdev property must be set");
         return false;
     }
-    memory_region_set_nonvolatile(mr, true);
+
+    /*
+     * FIXME: This code should eventually enumerate each memory region and
+     * report vmem and pmem capacity separate, but for now just set to one
+     */
+    memory_region_set_nonvolatile(mr, is_pmem);
     memory_region_set_enabled(mr, true);
     host_memory_backend_set_mapped(ct3d->hostmem, true);
 
@@ -123,7 +152,10 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
     address_space_init(&ct3d->hostmem_as, mr, name);
     g_free(name);
 
-    ct3d->cxl_dstate.pmem_size = ct3d->hostmem->size;
+    /* FIXME: When multiple regions are supported, this needs to aggregate */
+    ct3d->cxl_dstate.mem_size = ct3d->hostmem->size;
+    ct3d->cxl_dstate.vmem_size = is_pmem ? 0 : ct3d->hostmem->size;
+    ct3d->cxl_dstate.pmem_size = is_pmem ? ct3d->hostmem->size : 0;
 
     if (!ct3d->lsa) {
         error_setg(errp, "lsa property must be set");
@@ -272,6 +304,10 @@ static void ct3d_reset(DeviceState *dev)
 static Property ct3_props[] = {
     DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND,
                      HostMemoryBackend *),
+    DEFINE_PROP_LINK("persistent-memdev", CXLType3Dev, host_pmem,
+                     TYPE_MEMORY_BACKEND, HostMemoryBackend *),
+    DEFINE_PROP_LINK("volatile-memdev", CXLType3Dev, host_vmem,
+                     TYPE_MEMORY_BACKEND, HostMemoryBackend *),
     DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND,
                      HostMemoryBackend *),
     DEFINE_PROP_END_OF_LIST(),
@@ -340,7 +376,7 @@ static void ct3_class_init(ObjectClass *oc, void *data)
     pc->revision = 1;
 
     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
-    dc->desc = "CXL PMEM Device (Type 3)";
+    dc->desc = "CXL Memory Device (Type 3)";
     dc->reset = ct3d_reset;
     device_class_set_props(dc, ct3_props);
 
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 1e141b6621..fd96a5ea4e 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -117,8 +117,10 @@ typedef struct cxl_device_state {
         uint64_t host_set;
     } timestamp;
 
-    /* memory region for persistent memory, HDM */
+    /* memory region size, HDM */
+    uint64_t mem_size;
     uint64_t pmem_size;
+    uint64_t vmem_size;
 } CXLDeviceState;
 
 /* Initialize the register block for a device */
@@ -235,7 +237,10 @@ struct CXLType3Dev {
     PCIDevice parent_obj;
 
     /* Properties */
+    /* TODO: remove hostmem when multi-dev is implemented */
     HostMemoryBackend *hostmem;
+    HostMemoryBackend *host_vmem;
+    HostMemoryBackend *host_pmem;
     HostMemoryBackend *lsa;
 
     /* State */
-- 
2.37.3


  reply	other threads:[~2022-10-06 23:38 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-06 23:37 [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL Gregory Price
2022-10-06 23:37 ` Gregory Price [this message]
2022-10-10 15:25   ` [PATCH 2/2] hw/cxl: Allow CXL type-3 devices to be persistent or volatile Jonathan Cameron
2022-10-10 17:12   ` Davidlohr Bueso
2022-10-10 19:36     ` Davidlohr Bueso
2022-10-10 20:07       ` Gregory Price
2022-10-07 16:35 ` [PATCH 1/2] hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL Jonathan Cameron
2022-10-07 17:10 ` Davidlohr Bueso
2022-10-07 17:16 ` Davidlohr Bueso
2022-10-26 20:06 ` Michael S. Tsirkin
2022-10-26 20:09   ` Gregory Price
2022-10-26 20:11     ` Michael S. Tsirkin
2022-10-26 21:07       ` Gregory Price
2022-11-03 18:12         ` Jonathan Cameron

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