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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Alison Schofield <alison.schofield@intel.com>
Cc: Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
	<dan.j.williams@intel.com>, <ira.weiny@intel.com>,
	<vishal.l.verma@intel.com>
Subject: Re: [PATCH] cxl: update var names for interleave ways conversion macros
Date: Wed, 12 Oct 2022 13:45:50 +0100	[thread overview]
Message-ID: <20221012134550.00006e9b@huawei.com> (raw)
In-Reply-To: <Y0YV5G0TSG3zwKnB@aschofie-mobl2>

On Tue, 11 Oct 2022 18:18:28 -0700
Alison Schofield <alison.schofield@intel.com> wrote:

> On Tue, Oct 11, 2022 at 02:43:33PM -0700, Dave Jiang wrote:
> > Change var names for interleave ways macros to clearly indicate which
> > variable is encoded and which is the actual ways value.
> > 
> > iw == interleave ways
> > eniw == encoded interleave ways
> > 
> > Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> > ---
> >  drivers/cxl/cxl.h |   22 +++++++++++-----------
> >  1 file changed, 11 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> > index 7a4f740d710c..c0d826084465 100644
> > --- a/drivers/cxl/cxl.h
> > +++ b/drivers/cxl/cxl.h
> > @@ -78,14 +78,14 @@ static inline int cxl_to_granularity(u16 enig, unsigned int *ig)
> >  }
> >  
> >  /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */  
> 
> Above comment can be updated:
> CXL 8.2.4.19.7 CXL HDM Decoder n Control Register

Needs spec revision number.

CXL rev 3.0 8.2.4.....

J

  reply	other threads:[~2022-10-12 12:45 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-11 21:43 [PATCH] cxl: update var names for interleave ways conversion macros Dave Jiang
2022-10-12  1:15 ` Alison Schofield
2022-10-12 15:47   ` Dave Jiang
2022-10-12  1:18 ` Alison Schofield
2022-10-12 12:45   ` Jonathan Cameron [this message]
2022-10-12 15:47   ` Dave Jiang

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