[PATCH v4 00/10] hw/cxl: CXL emulation cleanups and minor fixes for upstream

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

Since V3:
- Rebased on upstream today.
- Refreshed DSDT.cxl due to changes upstream.
- Picked up tags from Gregory.

A small collection of misc fixes and tidying up pulled out from various
series. I've pulled this to the top of my queue of CXL related work
as they stand fine on their own and it will reduce the noise in
the larger patch sets if these go upstream first.

Gregory's patches were posted as part of his work on adding volatile support.
https://lore.kernel.org/linux-cxl/20221006233702.18532-1-gregory.price@memverge.com/
https://lore.kernel.org/linux-cxl/20221128150157.97724-2-gregory.price@memverge.com/
I might propose this for upstream inclusion this cycle, but testing is
currently limited by lack of suitable kernel support.

Ira's patches were part of his event injection series.
https://lore.kernel.org/linux-cxl/20221221-ira-cxl-events-2022-11-17-v2-0-2ce2ecc06219@intel.com/
Intent is to propose for upstream the rest of that series shortly after
some minor changes from earlier review.

My five patches have not previously been posted before this series.


Baseline: 6661b8c7fe "Merge tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu into staging"

Gregory Price (2):
  hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL
  hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition

Ira Weiny (3):
  qemu/bswap: Add const_le64()
  qemu/uuid: Add UUID static initializer
  hw/cxl/mailbox: Use new UUID network order define for cel_uuid

Jonathan Cameron (5):
  hw/mem/cxl_type3: Improve error handling in realize()
  hw/pci-bridge/cxl_downstream: Fix type naming mismatch
  tests/acpi: Allow update of q35/DSDT.cxl
  hw/i386/acpi: Drop duplicate _UID entry for CXL root bridge
  tests: acpi: Update q35/DSDT.cxl for removed duplicate UID

 hw/cxl/cxl-device-utils.c      |   2 +-
 hw/cxl/cxl-mailbox-utils.c     |  28 +++++++++++++++-------------
 hw/i386/acpi-build.c           |   1 -
 hw/mem/cxl_type3.c             |  15 +++++++++++----
 hw/pci-bridge/cxl_downstream.c |   2 +-
 include/hw/cxl/cxl_device.h    |   2 +-
 include/qemu/bswap.h           |  12 +++++++++++-
 include/qemu/uuid.h            |  12 ++++++++++++
 tests/data/acpi/q35/DSDT.cxl   | Bin 9578 -> 9564 bytes
 9 files changed, 52 insertions(+), 22 deletions(-)

-- 
2.37.2