From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Shesha Bhushan Sreenivasamurthy <sheshas@marvell.com>
Cc: "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"<\"qemu-devel@nongnu.org\"" <qemu-devel@nongnu.org>
Subject: Re: Concept of LD-ID in QEMU
Date: Thu, 8 Jun 2023 11:36:31 +0100 [thread overview]
Message-ID: <20230608113631.00007a53@Huawei.com> (raw)
In-Reply-To: <20230608113153.000033ef@Huawei.com>
Shesha,
You've sent an email with the 'In-reply-to' set to one of Terry's patches.
Please check why that happened and make sure you don't do that in future as
it hides your unrelated thread in email clients and the archives!
See
https://lore.kernel.org/linux-cxl/20230607221651.2454764-1-terry.bowman@amd.com/T/#t
for example
Jonathan
On Thu, 8 Jun 2023 11:31:53 +0100
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:
> On Wed, 7 Jun 2023 23:01:11 +0000
> Shesha Bhushan Sreenivasamurthy <sheshas@marvell.com> wrote:
>
> > Hi,
> > For DCD sideband there needs to be LD-ID. Is the following approach acceptable?
>
> QEMU question so +CC qemu-devel
>
> >
> > -device cxl-type3,bus=swport0,volatile-memdev=vmem0,dc-memdev=vmem1,id=cxl-vmem0,num-dc-regions=2,ldid=0 \
> > -device cxl-type3,bus=swport0,volatile-memdev=vmem1,dc-memdev=vmem2,id=cxl-vmem1,num-dc-regions=2,ldid=1 \
>
> Those will be PCI functions at this level so you can't do this until we have more advanced switch support
> (it has to know about multiple VHs - right now we only support fixed config switches). You could connect them
> to different switch ports - effectively that will be what it looks like when we do emulate a configurable switch.
>
> > -device i2c_mctp_cxl,bus=aspeed.i2c.bus.0,address=24,target=cxl-vmem0,cxl-vmem1")
> >
> > With this configuration, the same i2c device is handing both LDs and in FMAPI commands we use the LDID specified above.
>
> This effectively becomes a partial implementation of either an MLD or an MH-SLD
> To manage the actual memory access, those will almost certainly need a bunch of other shared
> infrastructure. So I'd ultimately expect the i2c_mctp_cxl device to target whatever
> device represents that shared infrastructure - it might be a separate device or a 'lead' type 3 device.
>
> So I'm not sure how this will fit together longer term. We need same infrastructure
> to work for a mailbox CCI on a MH-SLD/MLD as well and in that case there isn't a separate
> device to which we can provide multiple targets as you've done in your proposal here.
>
> So I think we need to work out how to handle all of (I've probably forgotten something)
> X marks done or in progress.
>
> X 1) i2c_mctp_cxl to an SLD (no PCI Mailbox definition for this one)
> 2) i2c_mctp_cxl directly to an MLD (your case)
> X 3) i2c_mctp_cxl to a fixed config switch (single fixed VH no MLD capable ports)
> X 4) PCI mailbox via switch CCI device that fixed config switch (no MLD capable ports)
> Even with this simple design some fun things you can do.
> 5) i2c_mctp_cxl to a configurable switch (probably a separate as yet to be defined management interface - that messes with hotplug)
> 6) PCI mailbox via switch CCI to configurable switch (again to defined management interface).
> 7) i2c_mctp_cxl to an MH-SLD - probably to which ever device also has support for
> tunneling to the FM owned LD via the PCI mailbox.
> X 8) PCI mailbox on MH-SLD tunneling to the FM owned LD.
> 9) i2c_mctp_cxl to an MH-MLD - similar to above - this one isn't that much more complex than MH-SLD case.
> X 10) PCI mailbox to MH-MLD - similar to above.
> 11) Tunneling via the switch CCI (then over PCI-VDM - though that detail isn't visible in QEMU) to an SLD
> 12) Tunneling via the switch CCI (then PCI-VDM) to an MH-SLD and on to he FM owned LD.
> 13) Tunneling via the switch CCI (then over PCI-VDM) to an MLD / MH-MLD
>
> Current i2c_mctp_cxl covers 1 and 3
> I'm part way through the tunnelling support for (8 and 100) - need to revisit and wire up the switch CCI PoC
> properly which will give us 4.
>
> 2 needs MLD support in general which we could maybe make work with a static binding in a switch but that
> would be odd - so we probably need to emulate a configurable switch for that
> 5,6 need configurable switch
> 7 needs same as 2 plus tunneling part similar to 4
> 9 again probably configurable switch for the MLD part to make sense
> 11 is fairly straight forward - but not done yet.
> 12 also not too bad, but needs the MH-SLD part to be fleshed out (some work on going )
> 13 needs pretty much everything defined.
>
> Trying to get the command line interface and device model right until we have PoC code
> for a few more cases is going to be at most a draft of what it might look like.
>
> So in short, lots to do. For now feel free to hack whatever you need in to be able
> to test the FM-API side of things, we can move that towards a clean command line definition
> once we have one figured out!
>
> Jonathan
>
>
> >
> > Thanks,
> > Shesha.
>
>
next prev parent reply other threads:[~2023-06-08 10:36 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-07 22:16 [PATCH v5 00/26] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-07 22:16 ` [PATCH v5 01/26] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-08 1:03 ` Dan Williams
2023-06-08 1:11 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 02/26] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-08 4:53 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 03/26] cxl: Rename member @dport of struct cxl_dport to @dev Terry Bowman
2023-06-08 6:42 ` Dan Williams
2023-06-08 14:36 ` Terry Bowman
2023-06-08 19:08 ` Dan Williams
2023-06-08 19:22 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 04/26] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-06-08 6:47 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 05/26] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-08 19:29 ` Dan Williams
2023-06-08 21:50 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 06/26] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-08 19:57 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 07/26] cxl/acpi: Moving add_host_bridge_uport() around Terry Bowman
2023-06-08 20:02 ` Dan Williams
2023-06-08 21:50 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 08/26] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-09 4:24 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 09/26] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-10 0:18 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 10/26] cxl/mem: Prepare for early RCH dport component register setup Terry Bowman
2023-06-10 0:26 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 11/26] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-10 1:36 ` Dan Williams
2023-06-10 1:44 ` Dan Williams
2023-06-12 20:39 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 12/26] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-10 2:18 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 13/26] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-10 2:23 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 14/26] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-07 23:01 ` Concept of LD-ID in QEMU Shesha Bhushan Sreenivasamurthy
2023-06-08 10:31 ` Jonathan Cameron
2023-06-08 10:36 ` Jonathan Cameron [this message]
2023-06-08 23:38 ` [EXT] " Shesha Bhushan Sreenivasamurthy
2023-06-09 11:20 ` Jonathan Cameron
2023-06-10 2:29 ` [PATCH v5 14/26] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Dan Williams
2023-06-07 22:16 ` [PATCH v5 15/26] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-06-10 2:34 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 16/26] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-10 2:36 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 17/26] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-10 2:37 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 18/26] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-06-10 2:38 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 19/26] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-10 3:09 ` Dan Williams
2023-06-12 14:41 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 20/26] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-10 3:11 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 21/26] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-10 3:12 ` Dan Williams
2023-06-12 21:12 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 22/26] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-10 3:23 ` Dan Williams
2023-06-12 18:19 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 23/26] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-12 20:29 ` Dan Williams
2023-06-13 15:28 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 24/26] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-12 21:38 ` Dan Williams
2023-06-16 16:17 ` Terry Bowman
2023-06-16 16:28 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 25/26] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-08 22:54 ` kernel test robot
2023-06-12 22:49 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 26/26] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-08 19:21 ` Bjorn Helgaas
2023-06-12 22:57 ` Dan Williams
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