From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>,
Dan Williams <dan.j.williams@intel.com>, <ira.weiny@intel.com>,
<vishal.l.verma@intel.com>, <alison.schofield@intel.com>
Subject: Re: [PATCH v7 10/11] cxl: Export sysfs attributes for memory device QoS class
Date: Thu, 22 Jun 2023 14:28:04 +0100 [thread overview]
Message-ID: <20230622142804.000011b4@Huawei.com> (raw)
In-Reply-To: <168695175866.3031571.16844903696610491673.stgit@djiang5-mobl3>
On Fri, 16 Jun 2023 14:42:38 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> Export qos_class sysfs attributes for the CXL memory device. The QoS clas
> should show up as /sys/bus/cxl/devices/memX/ram/qos_class for the volatile
> partition and /sys/bus/cxl/devices/memX/pmem/qos_class for the persistent
> partition. The QTG ID is retrieved via _DSM after supplying the
> calculated bandwidth and latency for the entire CXL path from device to
> the CPU. This ID is used to match up to the root decoder QoS class to
> determine which CFMWS the memory range of a hotplugged CXL mem device
> should be assigned under.
>
> While there may be multiple DSMAS exported by the device CDAT, the driver
> will only expose the first QTG ID per partition in sysfs for now. In the
> future when multiple QTG IDs are necessary, they can be exposed. [1]
>
> [1]: https://lore.kernel.org/linux-cxl/167571650007.587790.10040913293130712882.stgit@djiang5-mobl3.local/T/#md2a47b1ead3e1ba08f50eab29a4af1aed1d215ab
>
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>
I argue with myself inline. In the end I think you made right trade off
of complexity vs corner case handling.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index 057a43267290..89b8858f72b6 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -77,6 +77,37 @@ static ssize_t ram_size_show(struct device *dev, struct device_attribute *attr,
> static struct device_attribute dev_attr_ram_size =
> __ATTR(size, 0444, ram_size_show, NULL);
>
> +static int qos_class_sysfs_emit(struct qos_class *qos_class, char *buf)
> +{
> + int count, i;
> +
> + if (!qos_class)
> + return 0;
> +
> + for (i = 0, count = 0; i < qos_class->nr; i++) {
> + count += sysfs_emit_at(buf, count, "%d", qos_class->entries[i]);
> + count += sysfs_emit_at(buf, count, ", ");
> + }
> +
> + count -= 2;
> + count += sysfs_emit_at(buf, count, "\n");
Corner case fun.
If
count += sysfs_emit_at() butts up against the end of the buffer (would otherwise
overflow by 1) then you just pasted the \n one character earlier than desired and
ended up using only 4095 bytes of the 4k page.
Trivial but ugly ;)
I can see the complexity is here to avoid missing the \n in overflow condition
(which we don't expect on a sane system).
I guess it a fair trade off to loose a byte in the corner case.
> +
> + return count;
> +}
next prev parent reply other threads:[~2023-06-22 13:28 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-16 21:41 [PATCH v7 00/11] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-06-16 21:41 ` [PATCH v7 01/11] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-06-16 21:41 ` [PATCH v7 02/11] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-06-16 21:41 ` [PATCH v7 03/11] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-06-16 21:42 ` [PATCH v7 04/11] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-10-06 12:14 ` Jonathan Cameron
2023-10-06 22:45 ` [PATCH v8 " Dave Jiang
2023-10-07 0:07 ` [PATCH v9 " Dave Jiang
2023-06-16 21:42 ` [PATCH v7 05/11] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-06-16 21:42 ` [PATCH v7 06/11] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-06-16 21:42 ` [PATCH v7 07/11] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-06-16 21:42 ` [PATCH v7 08/11] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-06-16 21:42 ` [PATCH v7 09/11] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-06-16 21:42 ` [PATCH v7 10/11] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-06-22 13:28 ` Jonathan Cameron [this message]
2023-06-16 21:42 ` [PATCH v7 11/11] cxl/mem: Add debugfs output for QTG related data Dave Jiang
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