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From: Xiao Yang <yangx.jy@fujitsu.com>
To: nvdimm@lists.linux.dev
Cc: linux-cxl@vger.kernel.org, Xiao Yang <yangx.jy@fujitsu.com>
Subject: [NDCTL PATCH] cxl/region: Always use the correct target position
Date: Fri, 30 Jun 2023 23:12:45 +0800	[thread overview]
Message-ID: <20230630151245.1318-1-yangx.jy@fujitsu.com> (raw)

create_region() uses the wrong target position in some cases.
For example, cxl create-region command fails to create a new
region in 2 way interleave set when mem0 connects target1(position:1)
and mem1 connects target0(position:0):

$ cxl list -M -P -D -T -u
[
  {
    "ports":[
      {
        "port":"port1",
        "host":"pci0000:16",
        "depth":1,
        "nr_dports":1,
        "dports":[
          {
            "dport":"0000:16:00.0",
            "id":"0"
          }
        ],
        "memdevs:port1":[
          {
            "memdev":"mem0",
            "ram_size":"512.00 MiB (536.87 MB)",
            "serial":"0",
            "host":"0000:17:00.0"
          }
        ]
      },
      {
        "port":"port2",
        "host":"pci0000:0c",
        "depth":1,
        "nr_dports":1,
        "dports":[
          {
            "dport":"0000:0c:00.0",
            "id":"0"
          }
        ],
        "memdevs:port2":[
          {
            "memdev":"mem1",
            "ram_size":"512.00 MiB (536.87 MB)",
            "serial":"0",
            "host":"0000:0d:00.0"
          }
        ]
      }
    ]
  },
  {
    "root decoders":[
      {
        "decoder":"decoder0.0",
        "resource":"0x750000000",
        "size":"4.00 GiB (4.29 GB)",
        "interleave_ways":2,
        "interleave_granularity":8192,
        "max_available_extent":"4.00 GiB (4.29 GB)",
        "pmem_capable":true,
        "volatile_capable":true,
        "accelmem_capable":true,
        "nr_targets":2,
        "targets":[
          {
            "target":"pci0000:16",
            "alias":"ACPI0016:00",
            "position":1,
            "id":"0x16"
          },
          {
            "target":"pci0000:0c",
            "alias":"ACPI0016:01",
            "position":0,
            "id":"0xc"
          }
        ]
      }
    ]
  }
]

$ cxl create-region -t ram -d decoder0.0 -m mem0 mem1
cxl region: create_region: region0: failed to set target0 to mem0
cxl region: cmd_create_region: created 0 regions

Signed-off-by: Xiao Yang <yangx.jy@fujitsu.com>
---
 cxl/region.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/cxl/region.c b/cxl/region.c
index 07ce4a3..946b5ff 100644
--- a/cxl/region.c
+++ b/cxl/region.c
@@ -667,6 +667,8 @@ static int create_region(struct cxl_ctx *ctx, int *count,
 		struct json_object *jobj =
 			json_object_array_get_idx(p->memdevs, i);
 		struct cxl_memdev *memdev = json_object_get_userdata(jobj);
+		struct cxl_target *target = cxl_decoder_get_target_by_memdev(p->root_decoder,
+										memdev);
 
 		ep_decoder = cxl_memdev_find_decoder(memdev);
 		if (!ep_decoder) {
@@ -683,7 +685,7 @@ static int create_region(struct cxl_ctx *ctx, int *count,
 			try(cxl_decoder, set_mode, ep_decoder, p->mode);
 		}
 		try(cxl_decoder, set_dpa_size, ep_decoder, size/p->ways);
-		rc = cxl_region_set_target(region, i, ep_decoder);
+		rc = cxl_region_set_target(region, cxl_target_get_position(target), ep_decoder);
 		if (rc) {
 			log_err(&rl, "%s: failed to set target%d to %s\n",
 				devname, i, cxl_memdev_get_devname(memdev));
-- 
2.39.2


             reply	other threads:[~2023-06-30 15:14 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-30 15:12 Xiao Yang [this message]
2023-07-09 11:50 ` [NDCTL PATCH] cxl/region: Always use the correct target position Xiao Yang
2023-07-24 21:16   ` Verma, Vishal L

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