From: Terry Bowman <terry.bowman@amd.com>
To: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
<Jonathan.Cameron@huawei.com>, <linux-cxl@vger.kernel.org>
Cc: <terry.bowman@amd.com>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: [PATCH v8 14/14] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
Date: Fri, 30 Jun 2023 18:16:35 -0500 [thread overview]
Message-ID: <20230630231635.3132638-15-terry.bowman@amd.com> (raw)
In-Reply-To: <20230630231635.3132638-1-terry.bowman@amd.com>
From: Robert Richter <rrichter@amd.com>
Trivial change that renames variable phys_addr in
cxl_map_component_regs() to shorten its length to keep the 80 char
size limit for the line and also for consistency between the different
paths.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/regs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 2360b480c5c5..d22ba5a76b33 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -217,16 +217,16 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
for (i = 0; i < ARRAY_SIZE(mapinfo); i++) {
struct mapinfo *mi = &mapinfo[i];
- resource_size_t phys_addr;
+ resource_size_t addr;
resource_size_t length;
if (!mi->rmap->valid)
continue;
if (!test_bit(mi->rmap->id, &map_mask))
continue;
- phys_addr = map->resource + mi->rmap->offset;
+ addr = map->resource + mi->rmap->offset;
length = mi->rmap->size;
- *(mi->addr) = devm_cxl_iomap_block(dev, phys_addr, length);
+ *(mi->addr) = devm_cxl_iomap_block(dev, addr, length);
if (!*(mi->addr))
return -ENOMEM;
}
--
2.34.1
next prev parent reply other threads:[~2023-06-30 23:20 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-30 23:16 ` [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings Terry Bowman
2023-07-03 11:29 ` Jonathan Cameron
2023-06-30 23:16 ` [PATCH v8 02/14] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-30 23:16 ` [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-07-04 0:39 ` Dan Williams
2023-07-14 17:46 ` Robert Richter
2023-08-08 3:00 ` Dan Williams
2023-08-25 14:32 ` Robert Richter
2023-06-30 23:16 ` [PATCH v8 04/14] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-06-30 23:16 ` [PATCH v8 05/14] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-30 23:16 ` [PATCH v8 06/14] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-30 23:16 ` [PATCH v8 07/14] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-30 23:16 ` [PATCH v8 08/14] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-30 23:16 ` [PATCH v8 09/14] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-30 23:16 ` [PATCH v8 10/14] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-30 23:16 ` [PATCH v8 11/14] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-30 23:16 ` [PATCH v8 12/14] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-30 23:16 ` [PATCH v8 13/14] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-30 23:16 ` Terry Bowman [this message]
2023-07-01 0:20 ` [PATCH v8 00/14] cxl/pci: Add support for RCH RAS " Dan Williams
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