From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev
Cc: vishal.l.verma@intel.com
Subject: [NDCTL PATCH v4 4/4] ndctl: add test for qos_class in cxl-topology.sh
Date: Tue, 30 Jan 2024 16:32:44 -0700 [thread overview]
Message-ID: <20240130233526.1031801-5-dave.jiang@intel.com> (raw)
In-Reply-To: <20240130233526.1031801-1-dave.jiang@intel.com>
Add tests in cxl-topology.sh to verify qos_class are set with the fake
qos_class create by the kernel. Root decoders should have qos_class
attribute set. Memory devices should have ram_qos_class or pmem_qos_class
set depending on which partitions are valid.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
test/common | 4 ++++
test/cxl-topology.sh | 42 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/test/common b/test/common
index f1023ef20f7e..5694820c7adc 100644
--- a/test/common
+++ b/test/common
@@ -150,3 +150,7 @@ check_dmesg()
grep -q "Call Trace" <<< $log && err $1
true
}
+
+
+# CXL COMMON
+TEST_QOS_CLASS=42
diff --git a/test/cxl-topology.sh b/test/cxl-topology.sh
index e8b9f56543b5..d11a8cf11965 100644
--- a/test/cxl-topology.sh
+++ b/test/cxl-topology.sh
@@ -2,6 +2,45 @@
# SPDX-License-Identifier: GPL-2.0
# Copyright (C) 2022 Intel Corporation. All rights reserved.
+check_qos_decoders () {
+ # check root decoders have expected fake qos_class
+ # also make sure the number of root decoders equal to the number
+ # with qos_class found
+ json=$($CXL list -b cxl_test -D -d root)
+ decoders=$(echo "$json" | jq length)
+ count=0
+ while read -r qos_class
+ do
+ ((qos_class == TEST_QOS_CLASS)) || err "$LINENO"
+ count=$((count+1))
+ done <<< "$(echo "$json" | jq -r '.[] | .qos_class')"
+
+ ((count == decoders)) || err "$LINENO";
+}
+
+check_qos_memdevs () {
+ # Check that memdevs that expose ram_qos_class or pmem_qos_class have
+ # expected fake value programmed.
+ json=$(cxl list -b cxl_test -M)
+ readarray -t lines < <(jq ".[] | .ram_size, .pmem_size, .ram_qos_class, .pmem_qos_class" <<<"$json")
+ for (( i = 0; i < ${#lines[@]}; i += 4 ))
+ do
+ ram_size=${lines[i]}
+ pmem_size=${lines[i+1]}
+ ram_qos_class=${lines[i+2]}
+ pmem_qos_class=${lines[i+3]}
+
+ if [[ "$ram_size" != null ]]
+ then
+ ((ram_qos_class == TEST_QOS_CLASS)) || err "$LINENO"
+ fi
+ if [[ "$pmem_size" != null ]]
+ then
+ ((pmem_qos_class == TEST_QOS_CLASS)) || err "$LINENO"
+ fi
+ done
+}
+
. $(dirname $0)/common
rc=77
@@ -121,6 +160,8 @@ if (( bridges == 3 )); then
((count == 1)) || err "$LINENO"
fi
+check_min_kver "6.9" && check_qos_decoders
+
# check that all 8 or 10 cxl_test memdevs are enabled by default and have a
# pmem size of 256M, or 1G
json=$($CXL list -b cxl_test -M)
@@ -128,6 +169,7 @@ count=$(jq "map(select(.pmem_size == $pmem_size)) | length" <<< $json)
((bridges == 2 && count == 8 || bridges == 3 && count == 10 ||
bridges == 4 && count == 11)) || err "$LINENO"
+check_min_kver "6.9" && check_qos_memdevs
# check that switch ports disappear after all of their memdevs have been
# disabled, and return when the memdevs are enabled.
--
2.43.0
prev parent reply other threads:[~2024-01-30 23:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-30 23:32 ndctl: Add support of qos_class for CXL CLI Dave Jiang
2024-01-30 23:32 ` [NDCTL PATCH v4 1/4] ndctl: cxl: Add QoS class retrieval for the root decoder Dave Jiang
2024-01-30 23:32 ` [NDCTL PATCH v4 2/4] ndctl: cxl: Add QoS class support for the memory device Dave Jiang
2024-01-30 23:32 ` [NDCTL PATCH v4 3/4] ndctl: cxl: add QoS class check for CXL region creation Dave Jiang
2024-01-31 3:10 ` Alison Schofield
2024-01-30 23:32 ` Dave Jiang [this message]
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