[RFC PATCH 03/11] arm/virt: Add fw-first-ras property.

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

Provide a machine parameter to request firmware first RAS handling
and no hand over to the OS via _OSC.

Includes a bug fix as register access is not in CDW5 but only
in CXW4 (OS support field).

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 include/hw/arm/virt.h    |  1 +
 hw/acpi/cxl.c            |  3 ---
 hw/arm/virt-acpi-build.c |  1 +
 hw/arm/virt.c            | 20 ++++++++++++++++++++
 4 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 0a14551f19..84323ccb32 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -153,6 +153,7 @@ struct VirtMachineState {
     bool tcg_its;
     bool virt;
     bool ras;
+    bool fw_first_ras;
     bool mte;
     bool dtb_randomness;
     OnOffAuto acpi;
diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c
index 526cfe961a..1d6dadbddd 100644
--- a/hw/acpi/cxl.c
+++ b/hw/acpi/cxl.c
@@ -316,9 +316,6 @@ static Aml *__build_cxl_osc_method(bool fw_first)
     aml_append(if_cxl, aml_store(aml_name("CDW4"), aml_name("SUPC")));
     aml_append(if_cxl, aml_store(aml_name("CDW5"), aml_name("CTRC")));
 
-    /* CXL 2.0 Port/Device Register access */
-    aml_append(if_cxl,
-               aml_or(aml_name("CDW5"), aml_int(0x1), aml_name("CDW5")));
     aml_append(if_uuid, if_cxl);
 
     aml_append(if_uuid, aml_return(aml_arg(3)));
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index e5f6996111..cdc0bca729 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -208,6 +208,7 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
         .ecam   = memmap[ecam_id],
         .irq    = irq,
         .bus    = vms->bus,
+        .fw_first_ras = vms->fw_first_ras,
     };
 
     if (vms->highmem_mmio) {
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 14d3b66657..c1c8a514d7 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2864,6 +2864,20 @@ static void virt_set_ras(Object *obj, bool value, Error **errp)
     vms->ras = value;
 }
 
+static bool virt_get_fw_first_ras(Object *obj, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    return vms->fw_first_ras;
+}
+
+static void virt_set_fw_first_ras(Object *obj, bool value, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    vms->fw_first_ras = value;
+}
+
 static bool virt_get_mte(Object *obj, Error **errp)
 {
     VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -3400,6 +3414,12 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
                                           "Set on/off to enable/disable reporting host memory errors "
                                           "to a KVM guest using ACPI and guest external abort exceptions");
 
+    object_class_property_add_bool(oc, "fw-first-ras", virt_get_fw_first_ras,
+                                   virt_set_fw_first_ras);
+    object_class_property_set_description(oc, "fw-first-ras",
+                                          "Set on/off to control PCI/CXL _OSC allow the guest to"
+                                          "obtain permission to do native handling of AER and CXL errors");
+
     object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
     object_class_property_set_description(oc, "mte",
                                           "Set on/off to enable/disable emulating a "
-- 
2.39.2