From: Robert Richter <rrichter@amd.com>
To: Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
"Alison Schofield" <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: Robert Richter <rrichter@amd.com>, <linux-cxl@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v2] cxl: Fix use of phys_to_target_node() for x86
Date: Fri, 19 Apr 2024 16:01:09 +0200 [thread overview]
Message-ID: <20240419140109.1996590-1-rrichter@amd.com> (raw)
The CXL driver uses both functions phys_to_target_node() and
memory_add_physaddr_to_nid(). The x86 architecture relies on the
NUMA_KEEP_MEMINFO kernel option enabled for both functions to work
correct. Update Kconfig to make sure the option is always enabled for
the driver.
Suggested-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
---
drivers/cxl/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 67998dbd1d46..6140b3529a29 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -6,6 +6,7 @@ menuconfig CXL_BUS
select FW_UPLOAD
select PCI_DOE
select FIRMWARE_TABLE
+ select NUMA_KEEP_MEMINFO if (NUMA && X86)
help
CXL is a bus that is electrically compatible with PCI Express, but
layers three protocols on that signalling (CXL.io, CXL.cache, and
--
2.39.2
next reply other threads:[~2024-04-19 14:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-19 14:01 Robert Richter [this message]
2024-04-22 21:48 ` [PATCH v2] cxl: Fix use of phys_to_target_node() for x86 Ira Weiny
2024-04-23 0:19 ` Dan Williams
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