From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: "Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>
Cc: <kobayashi.da-06@jp.fujitsu.com>, <linux-cxl@vger.kernel.org>,
<y-goto@fujitsu.com>, <mj@ucw.cz>, <dan.j.williams@intel.com>
Subject: Re: [PATCH v11 2/2] cxl/pci: Add sysfs attribute for CXL 1.1 device link status
Date: Thu, 13 Jun 2024 16:08:17 +0100 [thread overview]
Message-ID: <20240613160817.0000520a@Huawei.com> (raw)
In-Reply-To: <20240612075940.92500-3-kobayashi.da-06@fujitsu.com>
On Wed, 12 Jun 2024 16:59:39 +0900
"Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com> wrote:
> Add sysfs attribute for CXL 1.1 device link status to the cxl pci device.
>
> In CXL1.1, the link status of the device is included in the RCRB mapped to
> the memory mapped register area. Critically, that arrangement makes the
> link status and control registers invisible to existing PCI user tooling.
>
> Export those registers via sysfs with the expectation that PCI user
> tooling will alternatively look for these sysfs files when attempting to
> access to these CXL 1.1 endpoints registers.
>
> Signed-off-by: "Kobayashi,Daisuke" <kobayashi.da-06@fujitsu.com>
LGTM
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
prev parent reply other threads:[~2024-06-13 15:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 7:59 [PATCH v11 0/2] Export cxl1.1 device link status register value to pci device sysfs Kobayashi,Daisuke
2024-06-12 7:59 ` [PATCH v11 1/2] cxl/core/regs: Add rcd_pcie_cap initialization Kobayashi,Daisuke
2024-06-13 15:07 ` Jonathan Cameron
2024-06-12 7:59 ` [PATCH v11 2/2] cxl/pci: Add sysfs attribute for CXL 1.1 device link status Kobayashi,Daisuke
2024-06-13 15:08 ` Jonathan Cameron [this message]
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