From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Huang Ying <ying.huang@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>,
"Alison Schofield" <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
"Alejandro Lucero" <alucerop@amd.com>
Subject: Re: [PATCH 3/3] cxl: Avoid to create dax regions for type2 accelerators
Date: Sun, 4 Aug 2024 17:38:13 +0100 [thread overview]
Message-ID: <20240804173813.00001018@Huawei.com> (raw)
In-Reply-To: <20240729084611.502889-4-ying.huang@intel.com>
On Mon, 29 Jul 2024 16:46:11 +0800
Huang Ying <ying.huang@intel.com> wrote:
> The memory range of a type2 accelerator should be managed by the type2
> accelerator specific driver instead of the common dax region drivers,
> as discussed in [1].
>
> [1] https://lore.kernel.org/linux-cxl/66469ff1b8fbc_2c2629427@dwillia2-xfh.jf.intel.com.notmuch/
>
> So, in this patch, we skip dax regions creation for type2 accelerator
> device memory regions.
>
> Based on: https://lore.kernel.org/linux-cxl/168592159835.1948938.1647215579839222774.stgit@dwillia2-xfh.jf.intel.com/
>
> Signed-off-by: "Huang, Ying" <ying.huang@intel.com>
> Co-developed-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> Cc: Davidlohr Bueso <dave@stgolabs.net>
> Cc: Jonathan Cameron <jonathan.cameron@huawei.com>
> Cc: Dave Jiang <dave.jiang@intel.com>
> Cc: Alison Schofield <alison.schofield@intel.com>
> Cc: Vishal Verma <vishal.l.verma@intel.com>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Cc: Alejandro Lucero <alucerop@amd.com>
> ---
> drivers/cxl/core/region.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 9a483c8a32fd..b37e12bb4a35 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -3435,6 +3435,14 @@ static int cxl_region_probe(struct device *dev)
> p->res->start, p->res->end, cxlr,
> is_system_ram) > 0)
> return 0;
> + /*
> + * HDM-D[B] (device-memory) regions have accelerator
> + * specific usage, skip device-dax registration.
> + */
> + if (cxlr->type == CXL_DECODER_DEVMEM)
> + return 0;
As in previous need to be careful as that may not mean it's
an accelerator.
However, we do need to deal with BI setup for HDM-DB type 3 devices
etc and to check the HDM Decoder capability registers to make sure
Supported Coherence model is appropriate. (e.g. 11 for host only or
device coherency - HDM-H/HDM-DB)
> +
> + /* HDM-H routes to device-dax */
> return devm_cxl_add_dax_region(cxlr);
> default:
> dev_dbg(&cxlr->dev, "unsupported region mode: %d\n",
next prev parent reply other threads:[~2024-08-04 16:38 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-29 8:46 [PATCH 0/3] cxl: Preparation of type2 accelerators support Huang Ying
2024-07-29 8:46 ` [PATCH 1/3] cxl: Set target type of root decoder based on CFMWS restrictions Huang Ying
2024-08-01 1:22 ` Alison Schofield
2024-08-04 16:24 ` Jonathan Cameron
2024-08-06 1:28 ` Huang, Ying
2024-08-12 20:59 ` Fan Ni
2024-07-29 8:46 ` [PATCH 2/3] cxl: Set target type of region with that of root decoder Huang Ying
2024-08-01 1:35 ` Alison Schofield
2024-08-01 6:28 ` Huang, Ying
2024-08-04 16:31 ` Jonathan Cameron
2024-08-12 21:00 ` Fan Ni
2024-07-29 8:46 ` [PATCH 3/3] cxl: Avoid to create dax regions for type2 accelerators Huang Ying
2024-08-04 16:38 ` Jonathan Cameron [this message]
2024-08-06 5:52 ` Huang, Ying
2024-08-12 11:50 ` Alejandro Lucero Palau
2024-08-12 11:54 ` Alejandro Lucero Palau
2024-08-15 1:10 ` Huang, Ying
2024-07-30 6:10 ` [PATCH 0/3] cxl: Preparation of type2 accelerators support Alejandro Lucero Palau
2024-07-30 6:34 ` Huang, Ying
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