[PATCH v2 0/2] Fix get a wrong pci host bridge in cxl_setup_parent_dport()

[Li Ming <ming4.li@intel.com>]

The cxl_test unit test environment on qemu always hit below call trace
with KASAN enabled:

 BUG: KASAN: slab-out-of-bounds in cxl_setup_parent_dport+0x480/0x530 [cxl_core]
 Read of size 1 at addr ff110000676014f8 by task (udev-worker)/676[   24.424403] CPU: 2 PID: 676 Comm: (udev-worker) Tainted: G           O     N 6.10.0-qemucxl #1
 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS edk2-20240214-2.el9 02/14/2024
 Call Trace:
  <TASK>
  dump_stack_lvl+0xea/0x150
  print_report+0xce/0x610
  ? kasan_complete_mode_report_info+0x40/0x200
  kasan_report+0xcc/0x110
  __asan_report_load1_noabort+0x18/0x20
  cxl_setup_parent_dport+0x480/0x530 [cxl_core]
  cxl_mem_probe+0x49b/0xaa0 [cxl_mem]

The root cause is that a wrong host bridge was gotten from
dport->dport_dev in cxl_setup_parent_dport(). In
cxl_setup_parent_dport(), it always calls
to_pci_host_bridge(dport->dport_dev) to get a pci_host_bridge structure.
There are two issues in the implementation:

* to_pci_host_bridge(dport->dport_dev) should be used only for RCH
  cases, dport->dport_dev points to a pci device rather than a pci host
  bridge in VH cases. The solution is checking if dport is in RCH mode
  then calling to_pci_host_bridge().
  (Patch 1)

* In cxl_test unit test environment, cxl_test will create a emulated CXL
  topology with emulated dports, the dport_dev of a emulated dport
  points to a platform device. to_pci_host_bridge(dport->dport_dev) also
  gets a wrong pci host bridge in the case. The solution is implementing
  a new wrap function called __wrap_cxl_setup_parent_dport() on cxl_test
  side, the function will filter all emulated dports, make sure only
  real dports can be handled by cxl_setup_parent_dport().
  (Patch 2)

v1 link: https://lore.kernel.org/linux-cxl/ZrHR+0w3bwM1Ik8h@xpf.sh.intel.com/T/#med6200e54ec12f09fdcc04571516adda261c9561

v2:
- Add call trace log into changelog
- Remove 'dev_is_platform(dport->dport_dev)' checking out of cxl driver
  scope. Check if dport is emulated in cxl_test.
  

Li Ming (2):
  cxl/pci: Get AER capability address from RCRB only for RCH dport
  cxl/test: Skip cxl_setup_parent_dport() for emulated dports

 drivers/cxl/core/pci.c        | 10 ++++++----
 tools/testing/cxl/Kbuild      |  1 +
 tools/testing/cxl/test/mock.c | 12 ++++++++++++
 3 files changed, 19 insertions(+), 4 deletions(-)

-- 
2.40.1