Re: [PATCH v2 15/15] efx: support pio mapping based on cxl

Jonathan Cameron
2024-08-27T15:23:58Z

On Mon, 19 Aug 2024 17:28:46 +0100
Alejandro Lucero Palau <alucerop@amd.com> wrote:

> On 8/4/24 19:13, Jonathan Cameron wrote:
> > On Mon, 15 Jul 2024 18:28:35 +0100
> > alejandro.lucero-palau@amd.com wrote:
> >
> >> From: Alejandro Lucero <alucerop@amd.com>
> >>
> >> With a device supporting CXL and successfully initialised, use the cxl
> >> region to map the memory range and use this mapping for PIO buffers.
> > This explains why you weren't worried about any step of the CXL
> > code failing and why that wasn't a 'bug' as such.
> >
> > I'd argue that you should still have the cxl intialization return
> > an error code and cleanup any state it if hits an error.
>
>
> Ideally, but with devm* being used, this is not easy to do if the error
> is not fatal.

That's usually a strong argument that you shouldn't use devm at that
level of abstraction.

>
>
> > Then the top level driver can of course elect to use an alternative
> > path given that failure. Logically it belongs there rather than relying
> > on a buffer being mapped or not.
> >
>
> Same driver needs to support same functionality which relies on those
> specific hardware buffers.
>
> The functionality is expected to be there with or without CXL. If the
> hardware has no CXL, the system or the device, the functionality will be
> there with legacy PCIe BAR regions. The green light for CXL use comes
> from two sources: the firmware and the kernel. Both need to give the
> thumbs up. If not, legacy PCIe BAR regions will be used.

Rather than going through full setup, see if you can figure out a minimal
(state free) check on whether it should work.

If a system is broken, then it's very different from a legacy system
with no support for CXL and we can maybe just handle the broken system
with errors (or quirks if it's a shipping system).

Jonathan

>