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Thu, 12 Sep 2024 02:08:38 -0700 Date: Thu, 12 Sep 2024 12:08:36 +0300 From: Zhi Wang To: Alejandro Lucero Palau CC: "Li, Ming4" , , , , , , , , , , Subject: Re: [PATCH v3 05/20] cxl: add function for type2 cxl regs setup Message-ID: <20240912120836.00003674.zhiw@nvidia.com> In-Reply-To: References: <20240907081836.5801-1-alejandro.lucero-palau@amd.com> <20240907081836.5801-6-alejandro.lucero-palau@amd.com> <68878cc6-addd-47a8-b6c7-9baa141a8b86@intel.com> Organization: NVIDIA X-Mailer: Claws Mail 4.2.0 (GTK 3.24.38; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E9:EE_|SN7PR12MB7419:EE_ X-MS-Office365-Filtering-Correlation-Id: 2df52340-02a2-499d-98d8-08dcd30a7ffb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 09:08:42.9315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2df52340-02a2-499d-98d8-08dcd30a7ffb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7419 On Tue, 10 Sep 2024 08:24:33 +0100 Alejandro Lucero Palau wrote: > > On 9/10/24 07:00, Li, Ming4 wrote: > > On 9/7/2024 4:18 PM, alejandro.lucero-palau@amd.com wrote: > >> From: Alejandro Lucero > >> > >> Create a new function for a type2 device initialising > >> cxl_dev_state struct regarding cxl regs setup and mapping. > >> > >> Signed-off-by: Alejandro Lucero > >> --- > >> drivers/cxl/core/pci.c | 30 > >> ++++++++++++++++++++++++++++++ drivers/net/ethernet/sfc/efx_cxl.c > >> | 6 ++++++ include/linux/cxl/cxl.h | 2 ++ > >> 3 files changed, 38 insertions(+) > >> > >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > >> index bf57f081ef8f..9afcdd643866 100644 > >> --- a/drivers/cxl/core/pci.c > >> +++ b/drivers/cxl/core/pci.c > >> @@ -1142,6 +1142,36 @@ int cxl_pci_setup_regs(struct pci_dev > >> *pdev, enum cxl_regloc_type type, } > >> EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); > >> > >> +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct > >> cxl_dev_state *cxlds) +{ > >> + struct cxl_register_map map; > >> + int rc; > >> + > >> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > >> + &cxlds->capabilities); > >> + if (!rc) { > >> + rc = cxl_map_device_regs(&map, > >> &cxlds->regs.device_regs); > >> + if (rc) > >> + return rc; > >> + } > >> + > >> + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > >> + &cxlds->reg_map, > >> &cxlds->capabilities); > >> + if (rc) > >> + dev_warn(&pdev->dev, "No component registers > >> (%d)\n", rc); + > >> + if (cxlds->capabilities & BIT(CXL_CM_CAP_CAP_ID_RAS)) { > >> + rc = cxl_map_component_regs(&cxlds->reg_map, > >> + > >> &cxlds->regs.component, > >> + > >> BIT(CXL_CM_CAP_CAP_ID_RAS)); > >> + if (rc) > >> + dev_dbg(&pdev->dev, "Failed to map RAS > >> capability.\n"); > >> + } > >> + > >> + return rc; > >> +} > >> +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, CXL); > >> + > > I thought this function should be implemented in efx driver, just > > like what cxl_pci driver does, because I think it is not a generic > > setup flow for all CXL type-2 devices. > > > > The idea here is to have a single function for discovering the > registers, both Device and Component registers. If an accel has not > all of them, as in the sfc case, not a problem with the last changes > added. > > Keeping with the idea of avoiding an accel driver to manipulate > cxl_dev_state, this accessor is created. > Agree. Let's keep this function. > > >> bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, u32 > >> expected_caps, u32 *current_caps) > >> { > >> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c > >> b/drivers/net/ethernet/sfc/efx_cxl.c index > >> bba36cbbab22..fee143e94c1f 100644 --- > >> a/drivers/net/ethernet/sfc/efx_cxl.c +++ > >> b/drivers/net/ethernet/sfc/efx_cxl.c @@ -66,6 +66,12 @@ int > >> efx_cxl_init(struct efx_nic *efx) goto err; > >> } > >> > >> + rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds); > >> + if (rc) { > >> + pci_err(pci_dev, "CXL accel setup regs failed"); > >> + goto err; > >> + } > >> + > >> return 0; > >> err: > >> kfree(cxl->cxlds); > >> diff --git a/include/linux/cxl/cxl.h b/include/linux/cxl/cxl.h > >> index 4a57bf60403d..f2dcba6cdc22 100644 > >> --- a/include/linux/cxl/cxl.h > >> +++ b/include/linux/cxl/cxl.h > >> @@ -5,6 +5,7 @@ > >> #define __CXL_H > >> > >> #include > >> +#include > >> > >> enum cxl_resource { > >> CXL_ACCEL_RES_DPA, > >> @@ -50,4 +51,5 @@ int cxl_set_resource(struct cxl_dev_state > >> *cxlds, struct resource res, enum cxl_resource); > >> bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, u32 > >> expected_caps, u32 *current_caps); > >> +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct > >> cxl_dev_state *cxlds); #endif > > >