[PATCH 15/15] cxl/pci: Enable internal CE/UCE interrupts for CXL PCIe port devices

[Terry Bowman <terry.bowman@amd.com>]

The AER service drivers and CXL drivers are updated to handle PCIe
port protocol errors. But, the PCIe AER correctable and uncorrectable
internal errors are mask disabled for the PCIe port devices.

Enable the AER internal errors for CXL PCIe port devices.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
 drivers/cxl/core/pci.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 4706113d2582..1d84a7022c4d 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -908,6 +908,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_port_err_detected, CXL);
 
 void cxl_uport_init_aer(struct cxl_port *port)
 {
+	struct pci_dev *pdev = to_pci_dev(port->uport_dev);
 	/* uport may have more than 1 downstream EP. Check if already mapped. */
 	if (port->uport_regs.ras) {
 		dev_warn(&port->dev, "RAS is already mapped\n");
@@ -920,12 +921,14 @@ void cxl_uport_init_aer(struct cxl_port *port)
 		dev_err(&port->dev, "Failed to map RAS capability.\n");
 		return;
 	}
+	pci_aer_unmask_internal_errors(pdev);
 }
 EXPORT_SYMBOL_NS_GPL(cxl_uport_init_aer, CXL);
 
 void cxl_dport_init_aer(struct cxl_dport *dport)
 {
 	struct device *dport_dev = dport->dport_dev;
+	struct pci_dev *pdev = to_pci_dev(dport_dev);
 
 	if (dport->rch) {
 		struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev);
@@ -949,6 +952,7 @@ void cxl_dport_init_aer(struct cxl_dport *dport)
 		dev_err(dport_dev, "Failed to map RAS capability.\n");
 		return;
 	}
+	pci_aer_unmask_internal_errors(pdev);
 }
 EXPORT_SYMBOL_NS_GPL(cxl_dport_init_aer, CXL);
 
-- 
2.34.1