From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, Ira Weiny <ira.weiny@intel.com>,
"Alejandro Lucero" <alucerop@amd.com>,
Dave Jiang <dave.jiang@intel.com>
Subject: Re: [PATCH v3 4/6] cxl: Make cxl_dpa_alloc() DPA partition number agnostic
Date: Tue, 4 Feb 2025 12:13:28 +0000 [thread overview]
Message-ID: <20250204121328.00006a0e@huawei.com> (raw)
In-Reply-To: <173864306400.668823.12143134425285426523.stgit@dwillia2-xfh.jf.intel.com>
On Mon, 03 Feb 2025 20:24:24 -0800
Dan Williams <dan.j.williams@intel.com> wrote:
> cxl_dpa_alloc() is a hard coded nest of assumptions around PMEM
> allocations being distinct from RAM allocations in specific ways when in
> practice the allocation rules are only relative to DPA partition index.
>
> The rules for cxl_dpa_alloc() are:
>
> - allocations can only come from 1 partition
>
> - if allocating at partition-index-N, all free space in partitions less
> than partition-index-N must be skipped over
>
> Use the new 'struct cxl_dpa_partition' array to support allocation with
> an arbitrary number of DPA partitions on the device.
>
> A follow-on patch can go further to cleanup 'enum cxl_decoder_mode'
> concept and supersede it with looking up the memory properties from
> partition metadata. Until then cxl_part_mode() temporarily bridges code
> that looks up partitions by @cxled->mode.
>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Reviewed-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Nice. More comments than questions in line....
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> @@ -542,15 +623,13 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled,
> int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size)
> {
> struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> - resource_size_t free_ram_start, free_pmem_start;
> struct cxl_port *port = cxled_to_port(cxled);
> struct cxl_dev_state *cxlds = cxlmd->cxlds;
> struct device *dev = &cxled->cxld.dev;
> - resource_size_t start, avail, skip;
> + struct resource *res, *prev = NULL;
> + resource_size_t start, avail, skip, skip_start;
> struct resource *p, *last;
> - const struct resource *ram_res = to_ram_res(cxlds);
> - const struct resource *pmem_res = to_pmem_res(cxlds);
> - int rc;
> + int part, rc;
>
> down_write(&cxl_dpa_rwsem);
> if (cxled->cxld.region) {
> @@ -566,47 +645,53 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size)
> goto out;
> }
>
> - for (p = ram_res->child, last = NULL; p; p = p->sibling)
> - last = p;
> - if (last)
> - free_ram_start = last->end + 1;
> - else
> - free_ram_start = ram_res->start;
> + part = -1;
> + for (int i = 0; i < cxlds->nr_partitions; i++) {
> + if (cxled->mode == cxl_part_mode(cxlds->part[i].mode)) {
> + part = i;
This code could be made simpler but you delete it in patch 5 anyway
so I'll drop my comments on it to avoid confusion.
I wrote a nice essay that will never see the light of day. Ah well.
> + break;
> + }
> + }
> +
> + if (part < 0) {
> + rc = -EBUSY;
> + goto out;
> + }
>
> - for (p = pmem_res->child, last = NULL; p; p = p->sibling)
> + res = &cxlds->part[part].res;
> + for (p = res->child, last = NULL; p; p = p->sibling)
> last = p;
> if (last)
> - free_pmem_start = last->end + 1;
> + start = last->end + 1;
> else
> - free_pmem_start = pmem_res->start;
> + start = res->start;
>
> - if (cxled->mode == CXL_DECODER_RAM) {
> - start = free_ram_start;
> - avail = ram_res->end - start + 1;
> - skip = 0;
> - } else if (cxled->mode == CXL_DECODER_PMEM) {
> - resource_size_t skip_start, skip_end;
> -
> - start = free_pmem_start;
> - avail = pmem_res->end - start + 1;
> - skip_start = free_ram_start;
> -
> - /*
> - * If some pmem is already allocated, then that allocation
> - * already handled the skip.
> - */
> - if (pmem_res->child &&
> - skip_start == pmem_res->child->start)
> - skip_end = skip_start - 1;
> - else
> - skip_end = start - 1;
> - skip = skip_end - skip_start + 1;
> - } else {
> - dev_dbg(dev, "mode not set\n");
> - rc = -EINVAL;
> - goto out;
> + /*
> + * To allocate at partition N, a skip needs to be calculated for all
> + * unallocated space at lower partitions indices.
> + *
> + * If a partition has any allocations, the search can end because a
> + * previous cxl_dpa_alloc() invocation is assumed to have accounted for
> + * all previous partitions.
> + */
> + skip_start = CXL_RESOURCE_NONE;
> + for (int i = part; i; i--) {
> + prev = &cxlds->part[i - 1].res;
> + for (p = prev->child, last = NULL; p; p = p->sibling)
> + last = p;
This pattern keeps turning up. Maybe a helper is appropriate?
last = resource_last_child()
Perhaps a job for another day.
> + if (last) {
> + skip_start = last->end + 1;
> + break;
> + }
> + skip_start = prev->start;
> }
>
> + avail = res->end - start + 1;
> + if (skip_start == CXL_RESOURCE_NONE)
> + skip = 0;
> + else
> + skip = res->start - skip_start;
> +
> if (size > avail) {
> dev_dbg(dev, "%pa exceeds available %s capacity: %pa\n", &size,
> cxl_decoder_mode_name(cxled->mode), &avail);
next prev parent reply other threads:[~2025-02-04 12:13 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-04 4:24 [PATCH v3 0/6] cxl: DPA partition metadata is a mess Dan Williams
2025-02-04 4:24 ` [PATCH v3 1/6] cxl: Remove the CXL_DECODER_MIXED mistake Dan Williams
2025-02-04 17:42 ` Fan Ni
2025-02-04 4:24 ` [PATCH v3 2/6] cxl: Introduce to_{ram,pmem}_{res,perf}() helpers Dan Williams
2025-02-04 11:30 ` Jonathan Cameron
2025-02-04 17:50 ` Fan Ni
2025-02-04 4:24 ` [PATCH v3 3/6] cxl: Introduce 'struct cxl_dpa_partition' and 'struct cxl_range_info' Dan Williams
2025-02-04 11:50 ` Jonathan Cameron
2025-02-04 18:50 ` Dan Williams
2025-02-04 4:24 ` [PATCH v3 4/6] cxl: Make cxl_dpa_alloc() DPA partition number agnostic Dan Williams
2025-02-04 12:13 ` Jonathan Cameron [this message]
2025-02-04 4:24 ` [PATCH v3 5/6] cxl: Kill enum cxl_decoder_mode Dan Williams
2025-02-04 12:23 ` Jonathan Cameron
2025-02-04 18:57 ` Dan Williams
2025-02-04 4:24 ` [PATCH v3 6/6] cxl: Cleanup partition size and perf helpers Dan Williams
2025-02-04 12:32 ` Jonathan Cameron
2025-02-04 20:52 ` Ira Weiny
2025-02-04 10:42 ` [PATCH v3 0/6] cxl: DPA partition metadata is a mess Alejandro Lucero Palau
2025-02-04 21:33 ` Dave Jiang
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