Re: [PATCH v1 1/1] cxl: add support for cxl reset

[kernel test robot <lkp@intel.com>]

Hi Srirangan,

kernel test robot noticed the following build warnings:

[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus linus/master v6.14-rc1 next-20250207]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Srirangan-Madhavan/cxl-add-support-for-cxl-reset/20250207-170511
base:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link:    https://lore.kernel.org/r/20250207090327.172478-2-smadhavan%40nvidia.com
patch subject: [PATCH v1 1/1] cxl: add support for cxl reset
config: x86_64-randconfig-161-20250208 (https://download.01.org/0day-ci/archive/20250208/202502081954.MzqpYilc-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-12) 11.3.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202502081954.MzqpYilc-lkp@intel.com/

smatch warnings:
drivers/pci/pci.c:5172 cxl_reset_prepare() warn: unsigned 'timeout_tot_us' is never less than zero.

vim +/timeout_tot_us +5172 drivers/pci/pci.c

  5124	
  5125	static int cxl_reset_prepare(struct pci_dev *dev, u16 dvsec)
  5126	{
  5127		u16 reg, val, cap;
  5128		int rc;
  5129		u32 timeout_us = 100, timeout_tot_us = 10000;
  5130	
  5131		/*
  5132		 * Wait for any pending transactions.
  5133		 * Assuming this does cxl.io stuff.
  5134		 */
  5135		if (!pci_wait_for_pending_transaction(dev))
  5136			pci_err(dev, "timed out waiting for pending transaction; performing cxl reset anyway\n");
  5137	
  5138		/*
  5139		 * Disable caching and then write back and invalidate lines.
  5140		 */
  5141		rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCAP,
  5142					  &cap);
  5143		if (rc)
  5144			return rc;
  5145	
  5146		if (!(cap & PCI_DVSEC_CXL_DEVCAP_CACHE_CAPABLE))
  5147			return 0;
  5148	
  5149		/*
  5150		 * Disable cache.
  5151		 * WB and invalidate cahce if capability is advertised.
  5152		 */
  5153		rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2,
  5154					  &reg);
  5155		if (rc)
  5156			return rc;
  5157		val = reg | PCI_DVSEC_CXL_DEVCTL2_DISABLE_CACHING;
  5158	
  5159		if (cap & PCI_DVSEC_CXL_DEVCAP_CACHE_WB_INVALIDATE)
  5160			val = reg | PCI_DVSEC_CXL_DEVCTL2_INIT_CACHE_WB_INVALIDATE;
  5161		pci_write_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2,
  5162				      val);
  5163	
  5164		/*
  5165		 * From Section 9.6: "Software may leverage the cache size reported in
  5166		 * the DVSEC CXL Capability2 register to compute a suitable timeout
  5167		 * value".
  5168		 * Given there is no conversion factor for cache size -> timeout,
  5169		 * setting timer for default 10ms.
  5170		 */
  5171		do {
> 5172			if (timeout_tot_us < 0)
  5173				return -ETIMEDOUT;
  5174			usleep_range(timeout_us, timeout_us+1);
  5175			timeout_tot_us -= timeout_us;
  5176			rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2,
  5177						  &reg);
  5178			if (rc)
  5179				return rc;
  5180		} while (!(reg & PCI_DVSEC_CXL_DEVSTATUS2_CACHE_INVALID));
  5181	
  5182		return 0;
  5183	}
  5184	

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