From: Li Ming <ming.li@zohomail.com>
To: dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, alison.schofield@intel.com,
vishal.l.verma@intel.com, ira.weiny@intel.com,
dan.j.williams@intel.com
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
Li Ming <ming.li@zohomail.com>
Subject: [PATCH v1 1/1] cxl/hdm: Verify HDM decoder capabilities after parsing
Date: Thu, 27 Feb 2025 18:32:51 +0800 [thread overview]
Message-ID: <20250227103251.390147-1-ming.li@zohomail.com> (raw)
devm_cxl_setup_hdm() only checks if decoder_count is 0 after parsing HDM
decoder capability, But according to the implementation of
cxl_hdm_decoder_count(), cxlhdm->decoder_count will never be 0.
Per CXL specification, the values ranges of decoder_count and
target_count are limited. Adding a checking for the values of them
in case hardware initialized them with wrong values.
Signed-off-by: Li Ming <ming.li@zohomail.com>
---
base-commit: 22eea823f69ae39dc060c4027e8d1470803d2e49 cxl/next
---
drivers/cxl/core/hdm.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 70cae4ebf8a4..a98191867c22 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -138,6 +138,34 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
return true;
}
+static int cxlhdm_decoder_caps_verify(struct cxl_hdm *cxlhdm)
+{
+ /*
+ * CXL r3.2 section 8.2.4.20.1
+ * CXL devices shall not advertise more than 10 decoders,
+ * CXL switches and HBs may advertise up to 32 decoders.
+ */
+ if (is_cxl_endpoint(cxlhdm->port) && cxlhdm->decoder_count > 10)
+ return -EINVAL;
+ else if (cxlhdm->decoder_count > 32)
+ return -EINVAL;
+
+ /*
+ * CXL r3.2 section 8.2.4.20.1
+ * target count is applicable only to CXL upstream port and HB.
+ * The number of target ports each decoder supports should be
+ * one of the numbers 1, 2, 4 or 8.
+ */
+ if (!is_cxl_endpoint(cxlhdm->port) &&
+ cxlhdm->target_count != 1 &&
+ cxlhdm->target_count != 2 &&
+ cxlhdm->target_count != 4 &&
+ cxlhdm->target_count != 8)
+ return -EINVAL;
+
+ return 0;
+}
+
/**
* devm_cxl_setup_hdm - map HDM decoder component registers
* @port: cxl_port to map
@@ -182,7 +210,8 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
}
parse_hdm_decoder_caps(cxlhdm);
- if (cxlhdm->decoder_count == 0) {
+ rc = cxlhdm_decoder_caps_verify(cxlhdm);
+ if (rc) {
dev_err(dev, "Spec violation. Caps invalid\n");
return ERR_PTR(-ENXIO);
}
--
2.34.1
next reply other threads:[~2025-02-27 10:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-27 10:32 Li Ming [this message]
2025-02-27 15:21 ` [PATCH v1 1/1] cxl/hdm: Verify HDM decoder capabilities after parsing Dave Jiang
2025-02-28 2:48 ` Li Ming
2025-02-27 21:47 ` Alison Schofield
2025-02-28 2:47 ` Li Ming
2025-02-28 18:34 ` Alison Schofield
2025-02-28 23:45 ` Dan Williams
2025-03-01 3:00 ` Li Ming
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