From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE01222D4C8 for ; Wed, 21 May 2025 18:34:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747852492; cv=none; b=ImhMClrJfCMr8sLEWSDXz4o6yIxXecQoUxnuQxo91UzlhV91U55y/20MEp/AdhMmAXq3Um2KcfACITKIy8tb3pyPSf8KKxRwpGBDMrUQU+G6bLm235Hpd/yNzzXI36I36+qXYmUM/nmDoOif4BCw6K7PWt76uxStM+sGWiU8Fq8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747852492; c=relaxed/simple; bh=MuRqHSpILASZwC9ezovXGjDmv3AjFWyIyH7HVe9i7sU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XIVpYEB3X/pMTNdMMXDHnwLHytGyS1HQSrHma9MjBkHACS39MDhxdorTgUQMntCGvAmXMXaufZ+6LdWGyWLgXdnm5e6uVw5itqNKGJkqmkZmnmSP5a4d5BWpD1wZxZkm9arxoPL89XOjvG2G5VIlzsgsCkcPKH1bqcPdipUyqbI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7741C4CEE4; Wed, 21 May 2025 18:34:52 +0000 (UTC) From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com, Gregory Price , Li Ming , Jonathan Cameron Subject: [PATCH v3 4/9] cxl: Remove adding of port_num via devm_cxl_add_dport() Date: Wed, 21 May 2025 11:34:38 -0700 Message-ID: <20250521183443.3828320-5-dave.jiang@intel.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250521183443.3828320-1-dave.jiang@intel.com> References: <20250521183443.3828320-1-dave.jiang@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit In preparation for delayed dport probing, remove setting of port_num through devm_cxl_add_dport(). Will temporarily set the port_num after dport is added for now. dport->port_num is set to CXL_DPORT_NUM_INVALID until the port_num is set in the dport->port_num field. Reviewed-by: Gregory Price Reviewed-by: Li Ming Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang --- v3: - Make note that port_num is set to default invalid value. (Alejandro) --- drivers/cxl/acpi.c | 7 ++++--- drivers/cxl/core/pci.c | 4 +++- drivers/cxl/core/port.c | 18 +++++++----------- drivers/cxl/cxl.h | 5 +++-- tools/testing/cxl/test/cxl.c | 5 +++-- tools/testing/cxl/test/mock.c | 5 ++--- 6 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index cb14829bb9be..6f8630e50800 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -593,16 +593,17 @@ static int add_host_bridge_dport(struct device *match, void *arg) if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11) { dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid, &ctx.base); - dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.uid, - ctx.base); + dport = devm_cxl_add_rch_dport(root_port, bridge, ctx.base); } else { - dport = devm_cxl_add_dport(root_port, bridge, ctx.uid, + dport = devm_cxl_add_dport(root_port, bridge, CXL_RESOURCE_NONE); } if (IS_ERR(dport)) return PTR_ERR(dport); + dport->port_num = ctx.uid; + ret = get_genport_coordinates(match, dport); if (ret) dev_dbg(match, "Failed to get generic port perf coordinates.\n"); diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 3b80e9a76ba8..3b84b43ab194 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -57,11 +57,13 @@ static int match_add_dports(struct pci_dev *pdev, void *data) dev_dbg(&port->dev, "failed to find component registers\n"); port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); - dport = devm_cxl_add_dport(port, &pdev->dev, port_num, map.resource); + dport = devm_cxl_add_dport(port, &pdev->dev, map.resource); if (IS_ERR(dport)) { ctx->error = PTR_ERR(dport); return PTR_ERR(dport); } + + dport->port_num = port_num; ctx->count++; return 0; diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 30a79276b489..d62008583da2 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1154,14 +1154,14 @@ static struct cxl_dport *cxl_alloc_dport(struct cxl_port *port, dport->dport_dev = dport_dev; dport->port = port; dport->id = id; + dport->port_num = CXL_DPORT_NUM_INVALID; return no_free_ptr(dport); } static struct cxl_dport * __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, - int port_num, resource_size_t component_reg_phys, - resource_size_t rcrb) + resource_size_t component_reg_phys, resource_size_t rcrb) { char link_name[CXL_TARGET_STRLEN]; struct cxl_dport *dport; @@ -1191,8 +1191,6 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, CXL_TARGET_STRLEN) return ERR_PTR(-EINVAL); - dport->port_num = port_num; - if (rcrb == CXL_RESOURCE_NONE) { rc = cxl_dport_setup_regs(&port->dev, dport, component_reg_phys); @@ -1253,7 +1251,6 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, * devm_cxl_add_dport - append VH downstream port data to a cxl_port * @port: the cxl_port that references this dport * @dport_dev: firmware or PCI device representing the dport - * @port_num: hardware identifier for this dport in a decoder's target list * @component_reg_phys: optional location of CXL component registers * * Note that dports are appended to the devm release action's of the @@ -1261,13 +1258,13 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, * switch ports) */ struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, - struct device *dport_dev, int port_num, + struct device *dport_dev, resource_size_t component_reg_phys) { struct cxl_dport *dport; - dport = __devm_cxl_add_dport(port, dport_dev, port_num, - component_reg_phys, CXL_RESOURCE_NONE); + dport = __devm_cxl_add_dport(port, dport_dev, component_reg_phys, + CXL_RESOURCE_NONE); if (IS_ERR(dport)) { dev_dbg(dport_dev, "failed to add dport to %s: %ld\n", dev_name(&port->dev), PTR_ERR(dport)); @@ -1284,13 +1281,12 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_add_dport, "CXL"); * devm_cxl_add_rch_dport - append RCH downstream port data to a cxl_port * @port: the cxl_port that references this dport * @dport_dev: firmware or PCI device representing the dport - * @port_num: hardware identifier for this dport in a decoder's target list * @rcrb: mandatory location of a Root Complex Register Block * * See CXL 3.0 9.11.8 CXL Devices Attached to an RCH */ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, - struct device *dport_dev, int port_num, + struct device *dport_dev, resource_size_t rcrb) { struct cxl_dport *dport; @@ -1300,7 +1296,7 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, return ERR_PTR(-EINVAL); } - dport = __devm_cxl_add_dport(port, dport_dev, port_num, + dport = __devm_cxl_add_dport(port, dport_dev, CXL_RESOURCE_NONE, rcrb); if (IS_ERR(dport)) { dev_dbg(dport_dev, "failed to add RCH dport to %s: %ld\n", diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index f4fe523aaf12..4ba3bbe9600b 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -345,6 +345,7 @@ enum cxl_decoder_type { #define CXL_DECODER_MAX_INTERLEAVE 16 #define CXL_QOS_CLASS_INVALID -1 +#define CXL_DPORT_NUM_INVALID -1 /** * struct cxl_decoder - Common CXL HDM Decoder Attributes @@ -754,10 +755,10 @@ struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, - struct device *dport, int port_num, + struct device *dport, resource_size_t component_reg_phys); struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, - struct device *dport_dev, int port_num, + struct device *dport_dev, resource_size_t rcrb); #ifdef CONFIG_PCIEAER_CXL diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index eb36408d287a..4846082127c4 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -968,11 +968,12 @@ static int mock_cxl_port_enumerate_dports(struct cxl_port *port) continue; } - dport = devm_cxl_add_dport(port, &pdev->dev, pdev->id, - CXL_RESOURCE_NONE); + dport = devm_cxl_add_dport(port, &pdev->dev, CXL_RESOURCE_NONE); if (IS_ERR(dport)) return PTR_ERR(dport); + + dport->port_num = pdev->id; } return 0; diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 6147f0966ffd..d9e8940d9328 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -246,7 +246,6 @@ EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dvsec_rr_decode, "CXL"); struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port, struct device *dport_dev, - int port_id, resource_size_t rcrb) { int index; @@ -254,14 +253,14 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port, struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); if (ops && ops->is_mock_port(dport_dev)) { - dport = devm_cxl_add_dport(port, dport_dev, port_id, + dport = devm_cxl_add_dport(port, dport_dev, CXL_RESOURCE_NONE); if (!IS_ERR(dport)) { dport->rcrb.base = rcrb; dport->rch = true; } } else - dport = devm_cxl_add_rch_dport(port, dport_dev, port_id, rcrb); + dport = devm_cxl_add_rch_dport(port, dport_dev, rcrb); put_cxl_mock_ops(index); return dport; -- 2.49.0