Re: [PATCH v4 6/9] cxl/test: Add mock version of devm_cxl_add_dport_by_dev()

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Tue, 24 Jun 2025 14:39:13 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> devm_cxl_add_dport_by_dev() outside of cxl_test is done through PCI
> hierarchy. However with cxl_test, it needs to be done through the
> platform device hierarchy. Add the mock function for
> devm_cxl_add_dport_by_dev().
> 
> When cxl_core calls a cxl_core exported function and that function is
> mocked by cxl_test, the call chain causes a circular dependency issue. Dan
> provided a workaround to avoid this issue. Apply the method to changes from
> the late dport allocation changes in order to enable cxl-test.
> 
> In cxl_core they are defined with "__" added in front of the function. A
> macro is used to define the original function names for when non-test
> version of the kernel is built. A bit of macros and typedefs are used to
> allow mocking of those functions in cxl_test.
> 
> Co-developed-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>

One comment inline.  I'm not fond of the macro dance in here but don't have
a better suggestion, so fair enough.

> index 5d6585d4b15e..b13f9796687c 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -1037,6 +1037,64 @@ static int mock_cxl_port_enumerate_dports(struct cxl_port *port)
>  	return 0;
>  }
>  
> +static struct cxl_dport *mock_cxl_add_dport_by_dev(struct cxl_port *port,
> +						   struct device *dport_dev)
> +{
> +	struct platform_device **array;
> +	int i, array_size;
> +
> +	if (port->depth == 1) {
> +		if (is_multi_bridge(port->uport_dev)) {
> +			array_size = ARRAY_SIZE(cxl_root_port);
> +			array = cxl_root_port;
> +		} else if (is_single_bridge(port->uport_dev)) {
> +			array_size = ARRAY_SIZE(cxl_root_single);
> +			array = cxl_root_single;
> +		} else {
> +			dev_dbg(&port->dev, "%s: unknown bridge type\n",
> +				dev_name(port->uport_dev));
> +			return ERR_PTR(-ENXIO);
> +		}

This is all duplicating code in mock_cxl_port_get_total_dports.  
Helper to at least get the array_size and array?  Probably not
worth combining the final loops.

> +	} else if (port->depth == 2) {
> +		struct cxl_port *parent = to_cxl_port(port->dev.parent);
> +
> +		if (is_multi_bridge(parent->uport_dev)) {
> +			array_size = ARRAY_SIZE(cxl_switch_dport);
> +			array = cxl_switch_dport;
> +		} else if (is_single_bridge(parent->uport_dev)) {
> +			array_size = ARRAY_SIZE(cxl_swd_single);
> +			array = cxl_swd_single;
> +		} else {
> +			dev_dbg(&port->dev, "%s: unknown bridge type\n",
> +				dev_name(port->uport_dev));
> +			return ERR_PTR(-ENXIO);
> +		}
> +	} else {
> +		dev_WARN_ONCE(&port->dev, 1, "unexpected depth %d\n",
> +			      port->depth);
> +		return ERR_PTR(-ENXIO);
> +	}
> +
> +	for (i = 0; i < array_size; i++) {
> +		struct platform_device *pdev = array[i];
> +
> +		if (pdev->dev.parent != port->uport_dev) {
> +			dev_dbg(&port->dev, "%s: mismatch parent %s\n",
> +				dev_name(port->uport_dev),
> +				dev_name(pdev->dev.parent));
> +			continue;
> +		}
> +
> +		if (&pdev->dev != dport_dev)
> +			continue;
> +
> +		return devm_cxl_add_dport(port, &pdev->dev, pdev->id,
> +					  CXL_RESOURCE_NONE);
> +	}
> +
> +	return ERR_PTR(-ENODEV);
> +}