From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B677202F8F for ; Wed, 9 Jul 2025 20:36:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752093385; cv=none; b=N5JGP77opwqYk3gAfZOkKO5O4/HE5VvxBsnfMiNozFMdWBePxiFYwR+c8OhStNndX1NqRVtml4sQG59VIUvgW/P7qy4NSTNUqWf2Lzs4bq3a5TcHo9xi+M2aJ3tr3p1gDGyVdx0ah0YBfHQem/4fqUzBVLgNRMD+doBOxNu4Ly8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752093385; c=relaxed/simple; bh=Usfyhek/cJcZTJq/YTn41nS51w+YT1nH1VVWdyRcR/Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=khI2LGWeZcI5c7K2fXD6dNaA8SbsLCORR6taoOOEjOaB+RSvGMmWQ1Vv1fNoTCkS9pyPCQ/6RdQ8UDKfk1GVd/x2Xm1yg+mk7G1+emYFzVnC/NqUNgYf5aGmdzD0i2/58rlMf45na25UdVahuy9kjQwjoaxX7fJ45GISzzwTJRw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0ED84C4CEEF; Wed, 9 Jul 2025 20:36:24 +0000 (UTC) From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com, Jonathan Cameron , Li Ming Subject: [PATCH v6 02/10] cxl: Add helper to detect top of CXL device topology Date: Wed, 9 Jul 2025 13:36:11 -0700 Message-ID: <20250709203619.2607133-3-dave.jiang@intel.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250709203619.2607133-1-dave.jiang@intel.com> References: <20250709203619.2607133-1-dave.jiang@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add a helper to replace the open code detection of CXL device hierarchy root. The helper will be used for delayed hostbridge port creation later on. Reviewed-by: Jonathan Cameron Reviewed-by: Li Ming Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang --- drivers/cxl/core/port.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index eb46c6764d20..a49491c14d19 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -39,6 +39,15 @@ DECLARE_RWSEM(cxl_region_rwsem); static DEFINE_IDA(cxl_port_ida); static DEFINE_XARRAY(cxl_root_buses); +/* + * The terminal device in PCI is NULL and @platform_bus + * for platform devices (for cxl_test) + */ +static bool is_cxl_hierarchy_head(struct device *dev) +{ + return (!dev || dev == &platform_bus); +} + int cxl_num_decoders_committed(struct cxl_port *port) { lockdep_assert_held(&cxl_region_rwsem); @@ -1635,11 +1644,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) struct device *uport_dev; struct cxl_dport *dport; - /* - * The terminal "grandparent" in PCI is NULL and @platform_bus - * for platform devices - */ - if (!dport_dev || dport_dev == &platform_bus) + if (is_cxl_hierarchy_head(dport_dev)) return 0; uport_dev = dport_dev->parent; -- 2.50.0