From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org
Cc: dave@stgolabs.net, jonathan.cameron@huawei.com,
alison.schofield@intel.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, dan.j.williams@intel.com
Subject: [PATCH v6 08/10] cxl: Create an xarray to tie a host bridge to the cxl_root
Date: Wed, 9 Jul 2025 13:36:17 -0700 [thread overview]
Message-ID: <20250709203619.2607133-9-dave.jiang@intel.com> (raw)
In-Reply-To: <20250709203619.2607133-1-dave.jiang@intel.com>
Add helper functions to setup association of a host bridge device to a
related cxl_root. Functions are in preparation to support the moving
of host bridge ports creation from cxl_acpi to cxl_memdev probe path.
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/port.c | 53 +++++++++++++++++++++++++++++++++++++++++
drivers/cxl/cxl.h | 4 ++++
2 files changed, 57 insertions(+)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index cc89141cddc8..2a80749a1994 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -38,6 +38,7 @@ DECLARE_RWSEM(cxl_region_rwsem);
static DEFINE_IDA(cxl_port_ida);
static DEFINE_XARRAY(cxl_root_buses);
+static DEFINE_XARRAY(cxl_root_ports);
/*
* The terminal device in PCI is NULL and @platform_bus
@@ -1014,6 +1015,58 @@ int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev,
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_register_pci_bus, "CXL");
+/**
+ * cxl_hb_uport_dev_to_root - Retrieve cxl_root tied to the host bridge device
+ * @hb_uport_dev: host bridge upstream port device
+ *
+ * Return cxl_root on success or NULL on failure
+ *
+ * A reference is taken on the port device. Caller needs to call put_device()
+ * when done.
+ */
+struct cxl_root *cxl_hb_uport_dev_to_root(struct device *hb_uport_dev)
+{
+ struct cxl_root *root;
+
+ root = xa_load(&cxl_root_ports, (unsigned long)hb_uport_dev);
+ if (!root)
+ return NULL;
+
+ get_device(&root->port.dev);
+
+ return root;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_hb_uport_dev_to_root, "CXL");
+
+static void unregister_hb_uport_root_ports(void *hb_uport_dev)
+{
+ xa_erase(&cxl_root_ports, (unsigned long)hb_uport_dev);
+}
+
+/**
+ * devm_cxl_register_hb_uport_root_port - Tie a hostbridge device to a root port
+ * @host: device that hosts the memory for the xarray entries
+ * @hb_uport_dev: host bridge device that serves as the xarray index
+ * @root: cxl_root that serves as the xarray entry data
+ *
+ * Return 0 on success or -errno on failure.
+ */
+int devm_cxl_register_hb_uport_root_port(struct device *host,
+ struct device *hb_uport_dev,
+ struct cxl_root *root)
+{
+ int rc;
+
+ rc = xa_insert(&cxl_root_ports, (unsigned long)hb_uport_dev, root,
+ GFP_KERNEL);
+ if (rc)
+ return rc;
+
+ return devm_add_action_or_reset(host, unregister_hb_uport_root_ports,
+ hb_uport_dev);
+}
+EXPORT_SYMBOL_NS_GPL(devm_cxl_register_hb_uport_root_port, "CXL");
+
static bool dev_is_cxl_root_child(struct device *dev)
{
struct cxl_port *port, *parent;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index cc5e0858824b..f88a7ab8d94b 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -734,6 +734,10 @@ struct pci_bus;
int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev,
struct pci_bus *bus);
struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
+int devm_cxl_register_hb_uport_root_port(struct device *host,
+ struct device *hb_uport_dev,
+ struct cxl_root *root);
+struct cxl_root *cxl_hb_uport_dev_to_root(struct device *uport_dev);
struct cxl_port *devm_cxl_add_port(struct device *host,
struct device *uport_dev,
resource_size_t component_reg_phys,
--
2.50.0
next prev parent reply other threads:[~2025-07-09 20:36 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-09 20:36 [PATCH v6 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-07-09 20:36 ` [PATCH v6 01/10] cxl/region: Add decoder check to check_commit_order() Dave Jiang
2025-07-09 20:36 ` [PATCH v6 02/10] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-07-09 20:36 ` [PATCH v6 03/10] cxl: Add helper to reap dport Dave Jiang
2025-07-11 2:21 ` Li Ming
2025-07-09 20:36 ` [PATCH v6 04/10] cxl: Defer dport allocation for switch ports Dave Jiang
2025-07-10 17:36 ` Li Ming
2025-07-10 20:55 ` Dave Jiang
2025-07-09 20:36 ` [PATCH v6 05/10] cxl/test: Add cxl_test support for cxl_port_update_total_ports() Dave Jiang
2025-07-11 2:22 ` Li Ming
2025-07-09 20:36 ` [PATCH v6 06/10] cxl/test: Add mock version of devm_cxl_add_dport_by_dev() Dave Jiang
2025-07-11 2:23 ` Li Ming
2025-07-09 20:36 ` [PATCH v6 07/10] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-07-09 20:36 ` Dave Jiang [this message]
2025-07-11 2:26 ` [PATCH v6 08/10] cxl: Create an xarray to tie a host bridge to the cxl_root Li Ming
2025-07-09 20:36 ` [PATCH v6 09/10] cxl: Move enumeration of hostbridge ports to the memdev probe path Dave Jiang
2025-07-11 2:46 ` Li Ming
2025-07-09 20:36 ` [PATCH v6 10/10] cxl: Remove devm_cxl_port_enumerate_dports() that is no longer used Dave Jiang
2025-07-11 2:27 ` Li Ming
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