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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF0000C37C.mail.protection.outlook.com (10.167.23.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.9031.11 via Frontend Transport; Tue, 12 Aug 2025 21:33:22 +0000 Received: from SCS-L-bcheatha.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 16:33:22 -0500 From: Ben Cheatham To: CC: Ben Cheatham Subject: [RFC PATCH 16/18] cxl/cache: Add cache device counting for CXL ports Date: Tue, 12 Aug 2025 16:29:19 -0500 Message-ID: <20250812212921.9548-17-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250812212921.9548-1-Benjamin.Cheatham@amd.com> References: <20250812212921.9548-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37C:EE_|IA0PR12MB8207:EE_ X-MS-Office365-Filtering-Correlation-Id: f7610d20-51f1-4db8-da78-08ddd9e7dd41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2025 21:33:22.8415 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f7610d20-51f1-4db8-da78-08ddd9e7dd41 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8207 Having more than one CXL.cache enabled device under a port requires CXL cache id capabilities (CXL 3.2 8.2.4.28/29). Add tracking of how many cache devices are under a port. If the required capabilities are absent and more than one device is enabled under the port, fail allocation of a cache id. Signed-off-by: Ben Cheatham --- drivers/cxl/cache.c | 42 ++++++++++++++++++++++++++++------------- drivers/cxl/core/port.c | 1 + drivers/cxl/cxl.h | 2 ++ 3 files changed, 32 insertions(+), 13 deletions(-) diff --git a/drivers/cxl/cache.c b/drivers/cxl/cache.c index fa3223165a18..886f9794472c 100644 --- a/drivers/cxl/cache.c +++ b/drivers/cxl/cache.c @@ -62,8 +62,12 @@ static int map_cache_idrt_cap(struct cxl_port *port) if (port->regs.cidrt) return 0; + /* + * A missing Cache ID Route Table capability is only an issue + * if there are multiple cache devices under the port + */ if (!port->reg_map.component_map.cidrt.valid) - return -ENXIO; + return port->cache_devs ? -ENXIO : 0; return cxl_map_component_regs(&port->reg_map, &port->regs.component, BIT(CXL_CM_CAP_CAP_ID_CIDRT)); @@ -71,19 +75,11 @@ static int map_cache_idrt_cap(struct cxl_port *port) static int map_cache_idd_cap(struct cxl_dport *dport) { - int agents; - if (dport->regs.cidd) return 0; - /* - * A missing Cache ID Decoder capability is only an issue - * if there are multiple cache agents in the VCS - */ - if (!dport->reg_map.component_map.cidd.valid) { - agents = atomic_read(&dport->port->cache_agents); - return agents > 1 ? -ENXIO : 0; - } + if (!dport->reg_map.component_map.cidd.valid) + return dport->port->cache_devs ? -ENXIO : 0; return cxl_map_component_regs(&dport->reg_map, &dport->regs.component, @@ -136,6 +132,19 @@ static int find_cache_id(struct cxl_cachedev *cxlcd) return devm_add_action_or_reset(&cxlcd->dev, free_cache_id, cstate); } +static void cxl_deactivate_cache(void *data) +{ + struct cxl_cachedev *cxlcd = data; + struct cxl_port *port = cxlcd->endpoint; + + for (port = cxlcd->endpoint; port && !is_cxl_root(port); + port = parent_port_of(port)) { + scoped_guard(device, &port->dev) { + port->cache_devs--; + } + } +} + static int devm_cxl_cachedev_allocate_cache_id(struct cxl_cachedev *cxlcd) { struct cxl_port *endpoint = cxlcd->endpoint, *port; @@ -167,9 +176,17 @@ static int devm_cxl_cachedev_allocate_cache_id(struct cxl_cachedev *cxlcd) rc = cxl_dport_program_cache_idd(dport, cxlcd); if (rc) return rc; + + port->cache_devs++; } - return 0; + if (!is_cxl_root(port)) { + cxl_deactivate_cache(cxlcd); + return -ENODEV; + } + + return devm_add_action_or_reset(&cxlcd->dev, cxl_deactivate_cache, + cxlcd); } static int find_snoop_gid(struct cxl_cachedev *cxlcd, u32 *gid) @@ -239,7 +256,6 @@ static int cxl_cache_probe(struct device *dev) if (rc) return rc; - return devm_cxl_cachedev_allocate_cache_id(cxlcd); } diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 3606ad557bfb..f9f1f0ff08c9 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -618,6 +618,7 @@ struct cxl_port *parent_port_of(struct cxl_port *port) return NULL; return port->parent_dport->port; } +EXPORT_SYMBOL_NS_GPL(parent_port_of, "CXL"); static void unregister_port(void *_port) { diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 9c475d8c1573..c67da9a378df 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -646,6 +646,7 @@ struct cxl_dax_region { * @cdat_available: Should a CDAT attribute be available in sysfs * @pci_latency: Upstream latency in picoseconds * @nr_hdmd: Number of HDM-D devices below port + * @cache_devs: Number of CXL.cache devices below this port */ struct cxl_port { struct device dev; @@ -672,6 +673,7 @@ struct cxl_port { bool cdat_available; long pci_latency; int nr_hdmd; + int cache_devs; }; /** -- 2.34.1