From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <linux-cxl@vger.kernel.org>
Cc: Ben Cheatham <Benjamin.Cheatham@amd.com>
Subject: [RFC PATCH 05/18] cxl: Change cxl_ep_load() to use struct device * parameter
Date: Tue, 12 Aug 2025 16:29:08 -0500 [thread overview]
Message-ID: <20250812212921.9548-6-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20250812212921.9548-1-Benjamin.Cheatham@amd.com>
Once cache devices are added the devices stored in cxl_ep refs will no
longer be gauranteed to be cxl_memdevs. Change cxl_ep_load() in
preparation of adding cache devices to the port hierarchy.
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
drivers/cxl/core/port.c | 4 ++--
drivers/cxl/core/region.c | 25 +++++++++++++------------
drivers/cxl/cxlmem.h | 4 ++--
drivers/cxl/port.c | 2 +-
4 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 0d27c9e8aa64..0eb406d4a131 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1532,7 +1532,7 @@ static int port_has_memdev(struct device *dev, const void *data)
if (port->depth != ctx->depth)
return 0;
- return !!cxl_ep_load(port, ctx->cxlmd);
+ return !!cxl_ep_load(port, &ctx->cxlmd->dev);
}
static void cxl_detach_ep(void *data)
@@ -1557,7 +1557,7 @@ static void cxl_detach_ep(void *data)
parent_port = to_cxl_port(port->dev.parent);
device_lock(&parent_port->dev);
device_lock(&port->dev);
- ep = cxl_ep_load(port, cxlmd);
+ ep = cxl_ep_load(port, &cxlmd->dev);
dev_dbg(&cxlmd->dev, "disconnect %s from %s\n",
ep ? dev_name(ep->ep) : "", dev_name(&port->dev));
cxl_ep_remove(port, ep);
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index ad60c93be803..9bd44cf4615e 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -257,8 +257,8 @@ static void cxl_region_decode_reset(struct cxl_region *cxlr, int count)
while (!is_cxl_root(to_cxl_port(iter->dev.parent)))
iter = to_cxl_port(iter->dev.parent);
- for (ep = cxl_ep_load(iter, cxlmd); iter;
- iter = ep->next, ep = cxl_ep_load(iter, cxlmd)) {
+ for (ep = cxl_ep_load(iter, &cxlmd->dev); iter;
+ iter = ep->next, ep = cxl_ep_load(iter, &cxlmd->dev)) {
struct cxl_region_ref *cxl_rr;
struct cxl_decoder *cxld;
@@ -319,8 +319,8 @@ static int cxl_region_decode_commit(struct cxl_region *cxlr)
if (rc) {
/* programming @iter failed, teardown */
- for (ep = cxl_ep_load(iter, cxlmd); ep && iter;
- iter = ep->next, ep = cxl_ep_load(iter, cxlmd)) {
+ for (ep = cxl_ep_load(iter, &cxlmd->dev); ep && iter;
+ iter = ep->next, ep = cxl_ep_load(iter, &cxlmd->dev)) {
cxl_rr = cxl_rr_load(iter, cxlr);
cxld = cxl_rr->decoder;
if (cxld->reset)
@@ -1005,7 +1005,8 @@ static int cxl_rr_ep_add(struct cxl_region_ref *cxl_rr,
struct cxl_port *port = cxl_rr->port;
struct cxl_region *cxlr = cxl_rr->region;
struct cxl_decoder *cxld = cxl_rr->decoder;
- struct cxl_ep *ep = cxl_ep_load(port, cxled_to_memdev(cxled));
+ struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
+ struct cxl_ep *ep = cxl_ep_load(port, &cxlmd->dev);
if (ep) {
rc = xa_insert(&cxl_rr->endpoints, (unsigned long)cxled, ep,
@@ -1080,7 +1081,7 @@ static int cxl_port_attach_region(struct cxl_port *port,
struct cxl_endpoint_decoder *cxled, int pos)
{
struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
- struct cxl_ep *ep = cxl_ep_load(port, cxlmd);
+ struct cxl_ep *ep = cxl_ep_load(port, &cxlmd->dev);
struct cxl_region_ref *cxl_rr;
bool nr_targets_inc = false;
struct cxl_decoder *cxld;
@@ -1257,7 +1258,7 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled,
}
cxled_peer = p->targets[pos - distance];
cxlmd_peer = cxled_to_memdev(cxled_peer);
- ep_peer = cxl_ep_load(port, cxlmd_peer);
+ ep_peer = cxl_ep_load(port, &cxlmd_peer->dev);
if (ep->dport != ep_peer->dport) {
dev_dbg(&cxlr->dev,
"%s:%s: %s:%s pos %d mismatched peer %s:%s\n",
@@ -1324,7 +1325,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
struct cxl_port *parent_port = to_cxl_port(port->dev.parent);
struct cxl_region_ref *cxl_rr = cxl_rr_load(port, cxlr);
struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
- struct cxl_ep *ep = cxl_ep_load(port, cxlmd);
+ struct cxl_ep *ep = cxl_ep_load(port, &cxlmd->dev);
struct cxl_region_params *p = &cxlr->params;
struct cxl_decoder *cxld = cxl_rr->decoder;
struct cxl_switch_decoder *cxlsd;
@@ -1573,8 +1574,8 @@ static void cxl_region_teardown_targets(struct cxl_region *cxlr)
while (!is_cxl_root(to_cxl_port(iter->dev.parent)))
iter = to_cxl_port(iter->dev.parent);
- for (ep = cxl_ep_load(iter, cxlmd); iter;
- iter = ep->next, ep = cxl_ep_load(iter, cxlmd))
+ for (ep = cxl_ep_load(iter, &cxlmd->dev); iter;
+ iter = ep->next, ep = cxl_ep_load(iter, &cxlmd->dev))
cxl_port_reset_targets(iter, cxlr);
}
}
@@ -1610,8 +1611,8 @@ static int cxl_region_setup_targets(struct cxl_region *cxlr)
* Descend the topology tree programming / validating
* targets while looking for conflicts.
*/
- for (ep = cxl_ep_load(iter, cxlmd); iter;
- iter = ep->next, ep = cxl_ep_load(iter, cxlmd)) {
+ for (ep = cxl_ep_load(iter, &cxlmd->dev); iter;
+ iter = ep->next, ep = cxl_ep_load(iter, &cxlmd->dev)) {
rc = cxl_port_setup_targets(iter, cxlr, cxled);
if (rc) {
cxl_region_teardown_targets(cxlr);
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 9c9d8a878785..f6af7276fa2e 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -112,12 +112,12 @@ int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info);
static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
- struct cxl_memdev *cxlmd)
+ struct device *cxldev)
{
if (!port)
return NULL;
- return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
+ return xa_load(&port->endpoints, (unsigned long)cxldev);
}
/*
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index b991c96622d7..7d88a8bec8e8 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -214,7 +214,7 @@ int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
down = iter, iter = to_cxl_port(iter->dev.parent)) {
struct cxl_ep *ep;
- ep = cxl_ep_load(iter, cxlmd);
+ ep = cxl_ep_load(iter, &cxlmd->dev);
ep->next = down;
}
--
2.34.1
next prev parent reply other threads:[~2025-08-12 21:30 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-12 21:29 [RFC PATCH 00/18] Initial CXL.cache device support Ben Cheatham
2025-08-12 21:29 ` [RFC PATCH 01/18] cxl/mem: Change cxl_memdev_ops to cxl_dev_ops Ben Cheatham
2025-08-12 21:29 ` [RFC PATCH 02/18] cxl: Move struct cxl_dev_state definition Ben Cheatham
2025-08-19 11:33 ` Jonathan Cameron
2025-08-22 18:00 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 03/18] cxl/core: Add CXL.cache device struct Ben Cheatham
2025-08-19 11:48 ` Jonathan Cameron
2025-08-22 18:00 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 04/18] cxl: Replace cxl_mem_find_port() with cxl_dev_find_port() Ben Cheatham
2025-08-12 21:29 ` Ben Cheatham [this message]
2025-08-12 21:29 ` [RFC PATCH 06/18] cxl/port, mem: Make adding an endpoint device type agnostic Ben Cheatham
2025-08-19 11:53 ` Jonathan Cameron
2025-08-22 18:00 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 07/18] cxl/port: Split endpoint port probe on device type Ben Cheatham
2025-08-19 11:57 ` Jonathan Cameron
2025-08-22 18:01 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 08/18] cxl/port: Update switch_port_probe() for CXL cache devices Ben Cheatham
2025-08-19 12:03 ` Jonathan Cameron
2025-08-22 18:01 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 09/18] cxl/core: Add function for getting CXL cache info Ben Cheatham
2025-08-12 21:29 ` [RFC PATCH 10/18] cxl/cache: Add cxl_cache driver Ben Cheatham
2025-08-19 12:11 ` Jonathan Cameron
2025-08-22 18:01 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 11/18] cxl/core: Add CXL snoop filter setup and checking Ben Cheatham
2025-08-19 14:18 ` Jonathan Cameron
2025-08-22 18:01 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 12/18] cxl/cache: Add CXL Cache ID Route Table mapping Ben Cheatham
2025-08-19 15:09 ` Jonathan Cameron
2025-08-22 18:01 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 13/18] cxl/cache: Implement Cache ID Route Table programming Ben Cheatham
2025-08-19 15:07 ` Jonathan Cameron
2025-08-22 18:01 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 14/18] cxl/cache: Add Cache ID Decoder capability mapping Ben Cheatham
2025-08-19 14:12 ` Alireza Sanaee
2025-08-22 18:01 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 15/18] cxl/cache: Implement Cache ID Decoder programming Ben Cheatham
2025-08-19 13:44 ` Alireza Sanaee
2025-08-20 8:55 ` Alireza Sanaee
2025-08-19 15:26 ` Jonathan Cameron
2025-08-22 18:01 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 16/18] cxl/cache: Add cache device counting for CXL ports Ben Cheatham
2025-08-19 15:30 ` Jonathan Cameron
2025-08-22 18:02 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 17/18] cxl/core: Add cache device attributes Ben Cheatham
2025-08-19 15:38 ` Jonathan Cameron
2025-08-22 18:02 ` Cheatham, Benjamin
2025-08-12 21:29 ` [RFC PATCH 18/18] cxl/core: Add cache device cache management attributes Ben Cheatham
2025-08-19 15:53 ` Jonathan Cameron
2025-08-22 18:02 ` Cheatham, Benjamin
2025-08-13 11:25 ` [RFC PATCH 00/18] Initial CXL.cache device support Alejandro Lucero Palau
2025-08-19 15:57 ` Jonathan Cameron
2025-08-19 16:05 ` Jonathan Cameron
2025-08-26 10:42 ` Alejandro Lucero Palau
2025-08-22 18:02 ` Cheatham, Benjamin
2025-08-26 10:44 ` Alejandro Lucero Palau
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