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Fri, 19 Sep 2025 11:21:32 +0000 (GMT) Date: Fri, 19 Sep 2025 16:51:27 +0530 From: Arpit Kumar To: Jonathan Cameron Cc: qemu-devel@nongnu.org, gost.dev@samsung.com, linux-cxl@vger.kernel.org, dave@stgolabs.net, vishak.g@samsung.com, krish.reddy@samsung.com, a.manzanares@samsung.com, alok.rathore@samsung.com, arpit.sysdev@gmail.com, cpgs@samsung.com Subject: Re: [PATCH v4 2/2] hw/cxl: Add Physical Port Control (Opcode 5102h) Message-ID: <20250919112127.moncriuj2fnatxl7@test-PowerEdge-R740xd> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <20250917172905.00005fa3@huawei.com> X-CMS-MailID: 20250919112134epcas5p1e778db12a690be6d26ab97bde4c76ad7 X-Msg-Generator: CA Content-Type: multipart/mixed; boundary="----M3TZWmnaQcCgpq3P2cdOV_lud716KtFuwxspURBH1dZsF.eH=_1d428_" CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250916080808epcas5p23113551a9a0719d68a8c3efff15209cc References: <20250916080736.1266083-1-arpit1.kumar@samsung.com> <20250916080736.1266083-3-arpit1.kumar@samsung.com> <20250917172905.00005fa3@huawei.com> ------M3TZWmnaQcCgpq3P2cdOV_lud716KtFuwxspURBH1dZsF.eH=_1d428_ Content-Type: text/plain; charset="utf-8"; format="flowed" Content-Disposition: inline On 17/09/25 05:29PM, Jonathan Cameron wrote: >On Tue, 16 Sep 2025 13:37:36 +0530 >Arpit Kumar wrote: > >> -added assert-deassert PERST implementation >> for physical ports (both USP and DSP's). >> -assert PERST involves bg operation for holding 100ms. >> -reset PPB implementation for physical ports. >> >> Signed-off-by: Arpit Kumar > >> @@ -4702,11 +4818,34 @@ static CXLRetCode cxl_set_phy_port_info(CXLCCI *cci) >> void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf, >> DeviceState *d, size_t payload_max) >> { >> + CXLUpstreamPort *pp; >> + uint8_t pn = 0; >> + >> cxl_copy_cci_commands(cci, cxl_cmd_set_sw); >> cci->d = d; >> cci->intf = intf; >> cxl_init_cci(cci, payload_max); >> cxl_set_phy_port_info(cci); >> + /* physical port control */ >> + pp = CXL_USP(cci->d); >This bit feels like it is wrongly located. I ran into this whilst >trying to add back the mctp variant as part of shuffling my cxl staging tree. > >Whilst this only gets used for the CCI commands, it is a USP thing not >a mailbox thing as we only want this called once per USP, not once per CCI on the >USP. > >Could we move this to a call from cxl_usp_realize? > >If something like that works would you mind sending me a patch on top of this >series to do so? I'm not yet set up to test this series so better you do it. > >We don't need that upstream until the first MCTP support on USP so this doesn't >block us on that front. > > >Thanks, >Jonathan > Hi Jonathan, Sure, will look into it as this seems tricky and then send a patch on top of this series. Also, it would be helpful if you have any suggestions for going about this change. Thanks, Arpit >> + for (int byte_index = 0; byte_index < (CXL_MAX_PHY_PORTS / BITS_PER_BYTE); >> + byte_index++) { >> + unsigned char byte = pp->pports.active_port_bitmask[byte_index]; >> + >> + for (int bit_index = 0; bit_index < 8; bit_index++, pn++) { >> + if (((byte) & (1 << bit_index)) != 0) { >> + qemu_mutex_init(&pp->pports.perst[pn].lock); >> + pp->pports.perst[pn].issued_assert_perst = false; >> + /* >> + * Assert PERST involves physical port to be in >> + * hold reset phase for minimum 100ms. No other >> + * physical port control requests are entertained >> + * until Deassert PERST command. >> + */ >> + pp->pports.perst[pn].asrt_time = ASSERT_WAIT_TIME_MS; >> + } >> + } >> + } >> } >> ------M3TZWmnaQcCgpq3P2cdOV_lud716KtFuwxspURBH1dZsF.eH=_1d428_ Content-Type: text/plain; charset="utf-8" ------M3TZWmnaQcCgpq3P2cdOV_lud716KtFuwxspURBH1dZsF.eH=_1d428_--