From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D35A51A2398; Tue, 7 Oct 2025 13:43:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759844608; cv=none; b=gIcPbWZgd27s79/U9ZcrldFLREU0O1tu+kG8RkRPO9b4roG8JEFpflLJiUFs1sS9WC0VVfYgSLyO6GdMjvEJWTlO13QL5NuAgMn+gceRjRCs6V3KLxmpCY26e2+BrwXVESS+Y42WgI5eGvBqzNcT+UHXqev2R8LqflvGETdbKb0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759844608; c=relaxed/simple; bh=TSfK4Sy1rGyqujpsRgnvtxRxemwN4XQivDCcvG7HInQ=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dQ43fmoo3thrIVs85Q1uz/uK7sjOxPaI60QzrIUTqupyuAIaCpsxT9mt/3XRRrKJFe5yiik7jl1pCkYBFQom/f11GfIxIVjvBSEZ+MxFV8s4xEhA2Q6orsrxQZ4Dv3FBLZ+K3Y2zNZJ2ORV8JapRvQojJXV6+xdbCbQfr63A9K8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4cgy2Y1gMzz6L54B; Tue, 7 Oct 2025 21:40:53 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id 49EBD140446; Tue, 7 Oct 2025 21:43:23 +0800 (CST) Received: from localhost (10.203.177.15) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 7 Oct 2025 14:43:22 +0100 Date: Tue, 7 Oct 2025 14:43:21 +0100 From: Jonathan Cameron To: CC: , , , , , , , , , Alejandro Lucero Subject: Re: [PATCH v19 11/22] cxl: Define a driver interface for HPA free space enumeration Message-ID: <20251007144321.0000778a@huawei.com> In-Reply-To: <20251006100130.2623388-12-alejandro.lucero-palau@amd.com> References: <20251006100130.2623388-1-alejandro.lucero-palau@amd.com> <20251006100130.2623388-12-alejandro.lucero-palau@amd.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml100012.china.huawei.com (7.191.174.184) To dubpeml100005.china.huawei.com (7.214.146.113) On Mon, 6 Oct 2025 11:01:19 +0100 alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero > > CXL region creation involves allocating capacity from Device Physical Address > (DPA) and assigning it to decode a given Host Physical Address (HPA). Before > determining how much DPA to allocate the amount of available HPA must be > determined. Also, not all HPA is created equal, some HPA targets RAM, some > targets PMEM, some is prepared for device-memory flows like HDM-D and HDM-DB, > and some is HDM-H (host-only). > > In order to support Type2 CXL devices, wrap all of those concerns into > an API that retrieves a root decoder (platform CXL window) that fits the > specified constraints and the capacity available for a new region. > > Add a complementary function for releasing the reference to such root > decoder. > > Based on https://lore.kernel.org/linux-cxl/168592159290.1948938.13522227102445462976.stgit@dwillia2-xfh.jf.intel.com/ > > Signed-off-by: Alejandro Lucero > Reviewed-by: Jonathan Cameron One thing I noticed on a fresh read through... > --- > drivers/cxl/core/region.c | 162 ++++++++++++++++++++++++++++++++++++++ > drivers/cxl/cxl.h | 3 + > include/cxl/cxl.h | 6 ++ > 3 files changed, 171 insertions(+) > > diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c > index e9bf42d91689..c5b66204ecde 100644 > --- a/drivers/cxl/core/region.c > +++ b/drivers/cxl/core/region.c > @@ -703,6 +703,168 @@ static int free_hpa(struct cxl_region *cxlr) > return 0; > } > > +struct cxlrd_max_context { > + struct device * const *host_bridges; > + int interleave_ways; > + unsigned long flags; > + resource_size_t max_hpa; > + struct cxl_root_decoder *cxlrd; > +}; > + > +static int find_max_hpa(struct device *dev, void *data) > +{ > + struct cxlrd_max_context *ctx = data; > + struct cxl_switch_decoder *cxlsd; > + struct cxl_root_decoder *cxlrd; > + struct resource *res, *prev; > + struct cxl_decoder *cxld; > + resource_size_t max; > + int found = 0; > + > + if (!is_root_decoder(dev)) > + return 0; > + > + cxlrd = to_cxl_root_decoder(dev); > + cxlsd = &cxlrd->cxlsd; > + cxld = &cxlsd->cxld; > + > + if ((cxld->flags & ctx->flags) != ctx->flags) { > + dev_dbg(dev, "flags not matching: %08lx vs %08lx\n", > + cxld->flags, ctx->flags); > + return 0; > + } > + > + for (int i = 0; i < ctx->interleave_ways; i++) { I think ctx->interleave_ways == 0 as it's never set, so found is never set, but then the check below succeeds as found == 0 and ctx->interleave_ways == 0 Definitely doesn't feel intentional! > + for (int j = 0; j < ctx->interleave_ways; j++) { > + if (ctx->host_bridges[i] == cxlsd->target[j]->dport_dev) { > + found++; > + break; > + } > + } > + } > + > + if (found != ctx->interleave_ways) { > + dev_dbg(dev, > + "Not enough host bridges. Found %d for %d interleave ways requested\n", > + found, ctx->interleave_ways); > + return 0; > + } > +} > + > +/** > + * cxl_get_hpa_freespace - find a root decoder with free capacity per constraints > + * @cxlmd: the mem device requiring the HPA > + * @interleave_ways: number of entries in @host_bridges > + * @flags: CXL_DECODER_F flags for selecting RAM vs PMEM, and Type2 device > + * @max_avail_contig: output parameter of max contiguous bytes available in the > + * returned decoder > + * > + * Returns a pointer to a struct cxl_root_decoder > + * > + * The return tuple of a 'struct cxl_root_decoder' and 'bytes available given > + * in (@max_avail_contig))' is a point in time snapshot. If by the time the > + * caller goes to use this decoder and its capacity is reduced then caller needs > + * to loop and retry. > + * > + * The returned root decoder has an elevated reference count that needs to be > + * put with cxl_put_root_decoder(cxlrd). > + */ > +struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_memdev *cxlmd, > + int interleave_ways, Currently unused. I think you mean to set the field in ctx > + unsigned long flags, > + resource_size_t *max_avail_contig) > +{ > + struct cxl_port *endpoint = cxlmd->endpoint; > + struct cxlrd_max_context ctx = { > + .flags = flags, > + }; > + struct cxl_port *root_port; > + > + if (!endpoint) { > + dev_dbg(&cxlmd->dev, "endpoint not linked to memdev\n"); > + return ERR_PTR(-ENXIO); > + } > + > + ctx.host_bridges = &endpoint->host_bridge; > + > + struct cxl_root *root __free(put_cxl_root) = find_cxl_root(endpoint); > + if (!root) { > + dev_dbg(&endpoint->dev, "endpoint is not related to a root port\n"); > + return ERR_PTR(-ENXIO); > + } > + > + root_port = &root->port; > + scoped_guard(rwsem_read, &cxl_rwsem.region) > + device_for_each_child(&root_port->dev, &ctx, find_max_hpa); > + > + if (!ctx.cxlrd) > + return ERR_PTR(-ENOMEM); > + > + *max_avail_contig = ctx.max_hpa; > + return ctx.cxlrd; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_get_hpa_freespace, "CXL");