Re: [PATCH v19 22/22] sfc: support pio mapping based on cxl

Jonathan Cameron
2025-10-07T14:48:50Z

On Mon, 6 Oct 2025 11:01:30 +0100
<alejandro.lucero-palau@amd.com> wrote:

> From: Alejandro Lucero <alucerop@amd.com>
>
> A PIO buffer is a region of device memory to which the driver can write a
> packet for TX, with the device handling the transmit doorbell without
> requiring a DMA for getting the packet data, which helps reducing latency
> in certain exchanges. With CXL mem protocol this latency can be lowered
> further.
>
> With a device supporting CXL and successfully initialised, use the cxl
> region to map the memory range and use this mapping for PIO buffers.
>
> Add the disabling of those CXL-based PIO buffers if the callback for
> potential cxl endpoint removal by the CXL code happens.
>
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>

A few minor things inline. The ifdef complexity in here is moderately
nasty though. Might be worth seeing if any of that can be moved
to stubs or IS_ENABLED() checks.

> diff --git a/drivers/net/ethernet/sfc/efx.h b/drivers/net/ethernet/sfc/efx.h
> index 45e191686625..057d30090894 100644
> --- a/drivers/net/ethernet/sfc/efx.h
> +++ b/drivers/net/ethernet/sfc/efx.h
> @@ -236,5 +236,4 @@ static inline bool efx_rwsem_assert_write_locked(struct rw_semaphore *sem)
>
> int efx_xdp_tx_buffers(struct efx_nic *efx, int n, struct xdp_frame **xdpfs,
> bool flush);
> -

stray change that you should clean out.

> #endif /* EFX_EFX_H */
> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
> index 79fe99d83f9f..a84ce45398c1 100644
> --- a/drivers/net/ethernet/sfc/efx_cxl.c
> +++ b/drivers/net/ethernet/sfc/efx_cxl.c
> @@ -11,6 +11,7 @@
> #include <cxl/pci.h>
> #include "net_driver.h"
> #include "efx_cxl.h"
> +#include "efx.h"
>
> #define EFX_CTPIO_BUFFER_SIZE SZ_256M
>
> @@ -20,6 +21,7 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
> struct pci_dev *pci_dev = efx->pci_dev;
> resource_size_t max_size;
> struct efx_cxl *cxl;
> + struct range range;
> u16 dvsec;
> int rc;
>
> @@ -119,19 +121,40 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
> cxl->efx_region = cxl_create_region(cxl->cxlrd, &cxl->cxled, 1);
> if (IS_ERR(cxl->efx_region)) {
> pci_err(pci_dev, "CXL accel create region failed");
> - cxl_put_root_decoder(cxl->cxlrd);
> - cxl_dpa_free(cxl->cxled);
> - return PTR_ERR(cxl->efx_region);
> + rc = PTR_ERR(cxl->efx_region);
> + goto err_dpa;

It's a somewhat trivial thing but you could reduce churn by
moving the err_dpa block introduction back to where this lot
was first added.

> + }
> +
> + rc = cxl_get_region_range(cxl->efx_region, &range);
> + if (rc) {
> + pci_err(pci_dev, "CXL getting regions params failed");
> + goto err_detach;
> + }
> +
> + cxl->ctpio_cxl = ioremap(range.start, range.end - range.start + 1);
> + if (!cxl->ctpio_cxl) {
> + pci_err(pci_dev, "CXL ioremap region (%pra) failed", &range);
> + rc = -ENOMEM;
> + goto err_detach;
> }
>
> probe_data->cxl = cxl;
> + probe_data->cxl_pio_initialised = true;
>
> return 0;
> +
> +err_detach:
> + cxl_decoder_detach(NULL, cxl->cxled, 0, DETACH_INVALIDATE);
> +err_dpa:
> + cxl_put_root_decoder(cxl->cxlrd);
> + cxl_dpa_free(cxl->cxled);
> + return rc;
> }
>
> void efx_cxl_exit(struct efx_probe_data *probe_data)
> {
> - if (probe_data->cxl) {
> + if (probe_data->cxl_pio_initialised) {
> + iounmap(probe_data->cxl->ctpio_cxl);
> cxl_decoder_detach(NULL, probe_data->cxl->cxled, 0,
> DETACH_INVALIDATE);
> cxl_dpa_free(probe_data->cxl->cxled);